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Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
We are looking for an FPGA Engineer to join our team and work on high-performance FPGA/SoC solutions, with a strong focus on digital signal processing (DSP), algorithms, and RF applications . Location This is a…
Hardware Engineer Intern contributing to FPGA development and hardware improvements at a global trading firm, using VHDL/Verilog and collaborating with trading and tech teams.
Design and verify custom silicon for Google’s TPU AI accelerators, leading CAD methodology and RTL design flows to power next-gen AI/ML systems.
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, bespoke training…
Designs and verifies PCIe subsystems and SoC infrastructure for Google’s next-gen TPUs, focusing on high-performance AI hardware acceleration.
Design verification engineer building and testing TPU silicon for Google’s AI/ML workloads using SystemVerilog and UVM.
Design verification engineer building silicon IP for Google’s AI accelerators and infrastructure, using SystemVerilog/UVM to verify ASIC blocks and close coverage for tape-out.
Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Lead verification of high-speed DSP pipelines for Google’s TPU AI accelerators, ensuring pre-silicon models match physical silicon behavior using SystemVerilog/UVM and emulation.
Designs and integrates custom ASICs for Apple’s SoCs using SystemVerilog, RTL, and synthesis while collaborating with hardware and software teams.
Senior engineer verifying next-gen microprocessor interconnects using SystemVerilog/UVM testbenches and industry tools to ensure functionality and performance before silicon tape-out.
Build ML models and synthetic data pipelines to improve chip-design workflows, collaborating across AI, hardware, and software teams.
Designs and verifies digital and mixed-signal SoCs using SystemVerilog/UVM, C, and assembly; builds UVM testbenches, assertions, and coverage models to ensure chip correctness.
Leads RTL microarchitecture design for an AI-focused company, defining hardware blocks and optimizing chip performance for machine-learning workloads.
Designs and verifies system-on-chip (SoC) testbenches for AI accelerators, ensuring correctness and performance in hardware development workflows.
Designs and verifies RTL (Register Transfer Level) logic for AI hardware accelerators using Verilog/VHDL and industry-standard EDA tools.
Designs and implements System-on-Chip verification environments and testbenches for AI hardware, using industry-standard methodologies and tools.
Lead RTL microarchitecture design for GPU, DSP, and AI accelerators in complex SoCs, optimizing performance, power, and area while guiding cross-functional teams.
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