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Staff FPGA Developer architecting reconfigurable logic for spacecraft avionics and payload systems, leading a real-time FPGA-based image processing pipeline for on-orbit detection and tracking using VHDL/Verilog.
Space is a warfighting domain. True Anomaly seeks those with the talent and ambition to build the technology that secures it. OUR MISSION True Anomaly delivers decisive capabilities for space superiority. We build…
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the…
Leads the design and development of advanced semiconductor package architectures for high-performance AI connectivity chips, collaborating with cross-functional teams to optimize electrical, thermal, and mechanical performance from concept to production.
Principal Field Applications Engineer at Astera Labs designs and supports AI infrastructure connectivity solutions for cloud providers and OEMs using CXL, Ethernet, PCIe, and related technologies.
Leads a Shanghai hardware design team to develop high-speed Active Electrical Cables and Smart Cable Modules for AI infrastructure, while providing local customer engineering support to China-based hyperscalers and OEMs.
Lead a new Taiwan hardware engineering hub to design validation platforms and rack-scale systems for AI connectivity, while partnering with OEMs across Asia to integrate Astera Labs’ silicon into their products.
Lead a hardware engineering team at a NASDAQ-listed AI connectivity company, designing high-speed cables, modules, and rack-scale systems while enabling OEM customers to integrate Astera Labs' silicon into their products.
Leads hardware manufacturing and operations for AI connectivity products, partnering with Asian contract manufacturers to scale production of cables, modules, and chassis systems while optimizing quality, cost, and time-to-market.
Hardware Lab Engineer at Astera Labs in San Jose sets up and maintains test environments for silicon validation of AI connectivity solutions like PCIe, CXL, and Ethernet, using high-speed test equipment and Python automation.
Junior engineer builds and runs test environments to verify next-gen AI connectivity chips using SystemVerilog/UVM and debugs hardware issues with design teams.
Leads a team of engineers to design advanced semiconductor packages (FCBGA/FCCSP, chiplet-based) for AI connectivity solutions, collaborating with OSATs and cross-functional teams using Cadence Allegro APD/SiP.
Designs and implements high-performance semiconductor chips for AI infrastructure, focusing on physical design flows, signoff, and automation in advanced process nodes.
Student role assisting senior engineers with physical design tasks for cutting-edge AI semiconductor chips, including synthesis, floorplanning, and verification using industry-standard EDA tools.
Principal Design Verification Engineer at Astera Labs designs and verifies advanced ASICs for AI infrastructure using SystemVerilog, UVM, and scripting languages, ensuring robust connectivity solutions for server and networking applications.
Principal Digital Design Engineer at Astera Labs designing high-performance AI connectivity silicon, owning RTL implementation through silicon bring-up for PCIe, CXL, and other protocols.
Principal Digital Design Engineer at Astera Labs designing high-performance connectivity solutions for AI infrastructure, using RTL, synthesis, and advanced CMOS nodes.
Principal Field Applications Engineer designs and supports AI connectivity solutions for cloud providers and OEMs, focusing on PCIe, Ethernet, and CXL technologies.
Designs power delivery systems and PCB layouts for ASIC-based AI connectivity hardware, using Cadence OrCAD/Allegro and collaborating with cross-functional teams.
Principal firmware engineer at Astera Labs, building and debugging C/Python code for CXL and DDR memory subsystems while acting as the technical liaison for hyperscale customers and OEMs.
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