Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Application Engineer – AI & Verification Solutions Location: PETAH TIKVA Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Application Engineer I: Systems Verification - Emulation Location: BELO HORIZONTE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of…
Design and build call-processing software and management systems for Windows using C#, .NET, C++, and VoIP/SIP protocols, following Agile practices.
Design and verify mission-critical FPGA firmware for high-power satellites, implementing real-time control, networking, and RF systems in VHDL/SystemVerilog.
Design and maintain embedded firmware for high-speed networking and semiconductor products, including drivers, HAL, and validation tools using C/C++ and hardware interfaces.
Physical design engineer implementing advanced ASICs from netlist to GDSII using PnR tools, focusing on timing closure, PPA optimization, and tape-out signoff.
Designs and automates ASIC front-end methodologies for IP/SoC projects, using EDA tools like SpyGlass and scripting in Python/Perl/TCL to improve design checks and integration flows.
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.
Validate high-speed I/O and PHY designs for FPGA silicon, including DDR/LPDDR and MIPI interfaces, using lab tools and automation.
Designs and runs SystemVerilog/UVM testbenches to verify FPGA IP blocks and SoC designs, using coverage-driven methods and assertions to ensure first-pass silicon success.
Design Verification Engineer builds UVM testbenches and runs pre-silicon verification for FPGA DFT logic like scan, MBIST, and JTAG to ensure silicon quality before tape-out.
Designs and develops advanced-node CMOS integrated circuit layouts, focusing on high-speed analog blocks like PLLs and ADCs while ensuring DRC/LVS compliance and minimizing parasitics.
Designs advanced-node CMOS IC layouts (PLL, ADC, regulators, etc.), ensuring DRC/LVS compliance, minimizing parasitics, and optimizing yield and performance.
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before…
Design and optimize physical design, STA, and power integrity flows for high-speed networking chips and SoCs using tools like PrimeTime and PrimePower.
Designs and optimizes semiconductor physical layouts for FPGAs, guiding RTL through GDSII with timing, power, and verification signoff.
We are looking for an FPGA Engineer to join our team and work on high-performance FPGA/SoC solutions, with a strong focus on digital signal processing (DSP), algorithms, and RF applications . Location This is a…
Designs and verifies advanced SRAM and analog/mixed-signal mask layouts for AMD’s processors, ensuring DRC/LVS compliance and collaborating with global teams to meet tape-out schedules.
We couldn't check your fit for this role — add a CV to your profile to see it next time.