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Design and verify secure hardware for space systems, assess FPGA/ASIC vulnerabilities, and develop guidance to mitigate threats in embedded and cyber-physical systems.
Engineer scalable compilation and synthesis flows for NVIDIA’s hardware emulation platforms, using EDA tools like Synopsys and Cadence to validate complex chip designs before fabrication.
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL coding, and PPA optimization from concept to silicon bring-up.
Leads a team to design and tape out next-gen processor and SoC IP, guiding RTL development, verification, and PPA optimization for high-performance, low-power ASICs.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
- B.Sc. in Electrical Engineering from a recognized university. - At least 10 years of proven hands-on experience in high-speed digital, power, and embedded system board design. - Extensive experience in schematic…
- 7+ years of UVM, C, System C, and scripting experience - Deep understanding of digital design principles, timing analysis, and power management techniques. Expertise in pre-silicon performance validation…
Lead the end-to-end integration of high-performance networking SoCs for AWS Nitro, defining IP blocks, resolving CDC/RDC issues, and driving synthesis/timing closure with Verilog/SystemVerilog and scripting.
Design and optimize custom silicon for AWS machine-learning servers, implementing high-performance RTL, microarchitecture, and trade-offs to power services like Inferentia.
Senior engineer designing and implementing FPGA-based hardware and firmware for AWS cloud servers, leading architecture, verification, and team mentorship.
Define firmware architecture and control interfaces for next-gen digital power management ICs used in AI, datacenters, and high-performance computing systems.
Designs and debugs FPGA firmware for high-speed RF/wireless systems, including DSP, JESD204C, and 100G Ethernet, using VHDL/Verilog and Python/C/C++.
Ingénieur en électronique - SPATIAL (H/F) Location: Toulouse, Occitanie, fr Description de l'entreprise Avec plus de 30 ans d’histoire, ALTEN accompagne en France et dans le monde entier la stratégie de…
Lead the design of camera and image-processing ASIC IP blocks using RTL, synthesis, and PPA analysis, while driving GenAI tools for hardware workflows and agentic AI solutions.
Designs and implements ASIC physical layouts for DSP cores used in mobile, compute, and AI products, handling floorplanning through tapeout.
Designs and verifies mixed-signal power-management ICs for compute, data center, automotive, and industrial systems using Cadence, Spectre, MATLAB, and Verilog/AMS.
Designs and optimizes System-on-Chip (SoC) architectures for mobile/IoT/XR platforms, focusing on performance, power, and security trade-offs.
Design verification engineer building UVM testbenches and test plans for USB controllers (USB3.2, USB2.0) to ensure compliance with industry standards.
Design Verification Engineer at Qualcomm verifies Bluetooth chipset designs using SystemVerilog/UVM, formal checks, and emulation to ensure hardware meets specifications before production.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Semiconductor innovation is accelerating faster than ever, driven by AI, advanced computing, automotive…
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