Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Design Verification Engineer at Qualcomm verifies Bluetooth chipset designs using SystemVerilog/UVM, formal checks, and emulation to ensure hardware meets specifications before production.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Semiconductor innovation is accelerating faster than ever, driven by AI, advanced computing, automotive…
Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled team developing cutting-edge silicon for GenAI workloads, where we push the…
Lead verification of complex SoC designs using SystemVerilog, UVM, and formal tools; mentor teams and drive coverage closure for memory-IP projects.
Designs ultra-low-latency FPGA-based systems for real-time trading acceleration using RTL and hardware design, working alongside experts in a research-driven finance firm.
Senior engineer verifying complex processor designs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness of Network-on-Chip IPs and SoCs.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Lead the verification of next-gen x86 CPU cores, architecting testbenches in SystemVerilog/C++ to validate cache, ISA, and low-power features for high-performance client processors.
Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Designs and optimizes FPGA/ASIC hardware for low-latency trading systems using SystemVerilog, RTL, and vendor tool suites.
Design Verification Engineer at Cerebras, building and testing the world's largest AI chip to ensure first-silicon success and ultra-fast AI inference.
Design Verification Engineer at AMD responsible for verifying custom hardware accelerators for servers, datacenters, and client/embedded markets using advanced ASIC verification techniques and methodologies like UVM and formal verification.
Staff Electrical and Electronic Design Engineer - Future Forward Location: Sunnyvale, CA, us Company Description It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly…
Lead a team designing next-generation HBM SoC logic dies for AI/ML, driving architecture, RTL implementation, and integration while optimizing performance, power, and area.
Design and validate next-gen NAND Flash memory chips, running Verilog simulations and AI-assisted tools to catch circuit flaws before and after silicon fabrication.
Develops FPGA-based security test infrastructure to validate DRAM resilience, mitigation effectiveness, and attack surfaces using Verilog/SystemVerilog, Python/C++, and AI-assisted tools like Claude.
Design Verification Engineer at NXP Semiconductors in Catania; builds and runs UVM/SystemVerilog test benches to validate complex semiconductor designs.
Junior engineer verifying semiconductor designs using SystemVerilog, UVM, and simulation tools to ensure functional correctness and reliability.
Design and verify next-gen memory chips, from full-chip functional checks to mixed-signal circuits and array architecture, using SystemVerilog, SPICE, and Cadence tools.
Principal RTL Design Engineer at Micron leads DRAM digital and mixed-signal IP development, owning RTL design from architecture to silicon-ready signoff while optimizing power, performance, and area.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
