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Разрабатывает цифровые алгоритмы обработки сигналов для ПЛИС Xilinx на SystemVerilog, переносит их из Matlab и оптимизирует под высокоскоростные интерфейсы.
Design Verification Engineer building custom silicon ASICs for YouTube video codecs using C/C++, HLS, SystemVerilog, and UVM to ensure hardware correctness and performance.
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating verification flows and debugging full-chip issues using SystemVerilog/UVM, Python, C/C++, and AI tools.
Design and verify mixed-signal system-on-chip circuits for wireless applications using SystemVerilog, VerilogAMS, and Python.
Staff engineer verifying next-gen eFPGA and SoC designs using UVM, SystemVerilog, and end-to-end silicon verification flows.
Designs and verifies RTL for AI-focused ASIC/SoC chips, integrating IP blocks and optimizing power, performance, and area for tapeout.
Responsibilities: Work closely with design engineers and architects to create and document detailed test plans for verifying the SoC design. Establish and manage the infrastructure and environment for automated…
Design and verify FPGA/ASIC digital circuits for aerospace/defense avionics, writing RTL in VHDL/Verilog and ensuring DO-254 compliance.
Verify GPU memory subsystem and interconnect IP designs using SystemVerilog/UVM, testplans, and coverage-driven flows to ensure correctness and performance.
Designs and implements ASIC physical design flows (RTL-to-GDS) using AI-assisted EDA tools, focusing on synthesis, timing closure, and tape-out verification.
Design and verify mixed-signal ICs for current sensing, using RTL, SystemVerilog, VHDL, and UVM to ensure first-pass silicon success.
Designs and verifies mixed-signal ICs, leading pre-tapeout simulations and regressions to ensure silicon meets specs and is manufacturable.
Lead the verification of next-gen x86 CPU cores, architecting testbenches and coverage plans for high-performance, low-power processor features in a global team.
Architect and implement DFx (Design for Test, Debug, etc.) methodologies and RTL for AMD’s AI-focused SoCs and ASICs, ensuring power, performance, and timing targets while collaborating across global teams.
The Future Forward group within Intuitive Surgical is searching for a Staff Electrical and Electronic Design Engineer to architect, design, and bring up the electronic hardware behind next-generation robotic and vision…
Develop FPGA-based digital designs for thermal cameras used in drones and navigation systems, implementing RTL in VHDL/Verilog and Ethernet protocols.
Design verification engineer building and debugging custom silicon for AI hardware using SystemVerilog, UVM, and formal tools.
Build and debug FPGA-based emulation platforms (Synopsys HAPS) to validate complex SoC/ASIC designs and enable early software execution before silicon tape-out.
Design and implement FPGA blocks for high-rate data transport and signal processing in satellite ground stations, using Verilog/SystemVerilog and Python.
Design and implement FPGA-based networking and DSP blocks for satellite ground stations, ensuring resilient, high-rate data links for real-time space communications.
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