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Designs and implements next-gen SSD controller ASICs, writing RTL, collaborating on verification, and optimizing flows with AI-assisted tools.
Design and run verification environments for next-gen eFPGA and SoC IP using UVM, SystemVerilog, and assertions to ensure silicon tape-out quality.
Lead the design, testing, and integration of FPGA firmware for high-performance imaging systems, collaborating with hardware and software teams to meet manufacturing requirements.
Design and maintain FPGA prototyping platforms (HAPS/Xilinx) and write C/C++ firmware tests for SoC verification, debugging silicon bring-up issues in the lab.
Design and verify custom silicon for Google’s TPU AI accelerators, focusing on management/control subsystems and SoC integration.
Senior FPGA Engineer, Cyber Location: Washington, District of Columbia, United States Department: AFS : Discovery Engineering : Cyber Anduril Industries is a defense technology company with a mission to transform U.S.…
Lead the roadmap for AMD’s FPGA/SoC simulation tools (UVM, SystemVerilog, HDL), RTL encryption, and deployment workflows, shaping verification methodologies and influencing industry standards.
Experienced Engineer - FPGA CAD Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Join our Team About this opportunity: You will join the FPGA CAD team to support design and…
Design and optimize ultra-low-latency FPGA firmware for high-frequency equities and futures trading systems using Xilinx and SystemVerilog.
Technical Marketing Engineer creating training, documentation, and demos for AMD’s Vivado FPGA tool suite, validating features and enabling customers through clear technical communication.
Design and implement verification environments for AMD’s Network-on-Chip IPs and SoCs using SystemVerilog/UVM, formal tools, and coverage-driven flows to ensure functional correctness.
Design and verify custom silicon for Google’s devices, building UVM testbenches and formal verification flows to ensure ASICs meet performance and reliability targets for AI and image-processing hardware.
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
Integrate RISC processors (RISC-V/Arm) into SoC platforms, configure subsystems, and collaborate on RTL, firmware, and system bring-up for Bitdeer’s Bitcoin mining and AI cloud hardware.
Designs and verifies digital sub-circuits for high-performance micro-controllers using Verilog/SystemVerilog, synthesis, and formal verification, collaborating with analog and software teams.
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating full-chip verification with SystemVerilog/UVM, Python, C/C++, and AI tools.
Lead FPGA architecture and RTL development for real-time medical systems, guiding Verilog/SystemVerilog implementations, timing closure, and hardware bring-up in a regulated healthcare environment.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Builds AI-native EDA tools and agent-driven workflows for chip design, writing Python/C++ code for Fortune enterprises and chip unicorns while translating user feedback into product updates.
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