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Designs and verifies FPGA logic for Microchip PolarFire SoCs using VHDL/Verilog, integrating with RISC-V cores and Linux/RTOS drivers.
Lead AI/ML-driven automation for ASIC design, optimizing power, performance, and area for SoCs using cutting-edge techniques like GenAI and reinforcement learning.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
An intern designs ultra-low-latency FPGA systems for trading infrastructure, working with hardware design, RTL, and performance optimization alongside a small engineering team.
Develops GPU applications and emulation tools to verify AMD’s pre-silicon hardware for AI/ML and HPC workloads, focusing on debugging, benchmarking, and performance analysis.
Leads a team specializing in hardware/firmware co-verification for AMD’s security IP subsystems, including cryptography, compression, and DMA accelerators, using UVM/SystemVerilog and FPGA prototypes. Focuses on verification architecture, performance optimization, and team management for next-gen SoCs.
Intern designs FPGA/ASIC hardware for ultra-low latency trading systems, coding in SystemVerilog/Python and bringing designs to life on real silicon.
Build and optimize diagnostics software to validate AMD’s security hardware IP across CPUs, GPUs, and accelerators, using C/C++ and AI-driven tools to root-cause issues from pre-silicon to production.
Designs and validates high-performance digital boards and FPGA firmware for advanced electronic warfare and secure communications systems, from concept to production.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Design and integrate RTL for mixed-signal power management IP, drive timing closure, and tape-out while collaborating with analog, firmware, and physical design teams.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
Develops and maintains emulation infrastructure for Google Cloud’s TPU hardware, focusing on verifying complex digital designs and debugging emulation platforms to accelerate AI/ML hardware acceleration.
Core Debug Engineer at AMD verifies next-gen microprocessor designs, collaborates with RTL engineers, and resolves complex logic bugs to ensure functionality and architectural compliance.
Configure and integrate RISC processor IP into SoC platforms, customize processor features, develop RTL wrappers and system glue logic, integrate interconnects and interrupt controllers, support verification and system…
The role develops and integrates PCIe-related IP blocks, evaluates performance, supports verification closure and functional coverage, debugs pre-silicon and post-silicon issues, and contributes to software development…
Integrate commercial RISC-V core soft IP with external accelerators, tailor CPU features to meet performance, power, and area requirements, modify Verilog and SystemVerilog RTL, collaborate across ASIC design…
Join Bitdeer's IC development team to ensure the functional correctness and performance of computer arithmetic IPs. Develop comprehensive verification environments, execute test plans, debug RTL issues, and…
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