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Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Build and optimize simulation infrastructure for NVIDIA’s next-gen networking silicon, accelerating full-chip verification with SystemVerilog/UVM, Python, C/C++, and AI tools.
Lead FPGA architecture and RTL development for real-time medical systems, guiding Verilog/SystemVerilog implementations, timing closure, and hardware bring-up in a regulated healthcare environment.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Builds AI-native EDA tools and agent-driven workflows for chip design, writing Python/C++ code for Fortune enterprises and chip unicorns while translating user feedback into product updates.
Design and implement FPGA firmware for next-gen radar and sensing systems, integrating with software and hardware for defense and commercial applications.
Design and implement FPGA-based digital signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused product company.
Design and implement FPGA-based signal processing for next-gen radar and sensing systems, integrating with software and hardware in a defense-focused R&D environment.
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
Leads RTL design for Google’s custom silicon solutions, focusing on ASIC development for SoC/VLSI, Verilog/SystemVerilog coding, and hardware-software integration to power Google Cloud and consumer products like Vertex AI.
Logic Design Engineer Location: Israel - Haifa (IL) Description Chips Talk, We Listen proteanTecs is a game-changing startup that's giving advanced electronics the power to report on their own health. In a digital…
Design and optimize FPGA systems to reduce latency and boost throughput for a proprietary trading firm, using SystemVerilog and automated verification.
Lead the RTL design and microarchitecture of an ultra-low-power SoC for edge AI/IoT, defining dataflow fabrics, memory subsystems, and interconnects using SystemVerilog and collaborating across hardware, firmware, and verification teams.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on high-performance RTL code and cross-functional integration with verification and physical design teams.
Lead a team to architect and implement FPGA-based signal processing systems for a space-based cellular broadband network, using VHDL/Verilog and Xilinx tools.
With our groundbreaking satellite 5G constellation, OQ Technology is a global leader in IoT communication connectivity and associated services. We are a venture capital-backed company with a successful track record of…
Engineer I – Focal Plane Electronics Systems Location: Boulder, Colorado, United States Category: Engineering & Technology Employment Type: Full-Time Job Description We are seeking an early‑career Focal Plane…
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/VHDL and ASIC flows.
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
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