AMD's SerDes Technology team is hiring an RTL design engineer to develop high-performance, multi-protocol wireline transceivers in advanced CMOS processes. Day to day, the engineer micro-architects and codes digital SerDes blocks (calibration loops, DSP, clock-data recovery) in Verilog/SystemVerilog, verifies functionality, runs LINT/CDC checks, closes static timing, and supports silicon bring-up.
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