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Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/VHDL and ASIC flows.
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Staff Design Verification Engineer to verify high-performance CPU cores (frontend, midcore, load-store, prefetch) using SystemVerilog/UVM, debug microarchitectural issues, and drive coverage closure for next-gen RISC-V processors.
Own verification of high-performance CPU cores using SystemVerilog/UVM, writing test plans, assertions, and coverage to catch corner-case bugs in out-of-order pipelines.
Design and run verification tests for CPU cache and memory subsystems, focusing on coherency, ordering, and corner-case bugs using SystemVerilog/UVM.
Staff engineer verifying CPU cache and memory-subsystem designs using SystemVerilog/UVM, focusing on cache coherency, ordering, and corner-case bugs.
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
Designs and runs SystemVerilog/UVM testbenches to verify Arm-based CPUs, PCIe, DDR, and SoC subsystems, writing C/C++/Assembly tests and debugging RTL issues.
Designs and implements high-performance RISC-V CPU and SoC RTL modules using SystemVerilog, collaborating with architects, verification, and backend teams to optimize performance, power, and area.
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
Designs and verifies mixed-signal SoCs for wireless systems, building analog/system models and testbenches in SystemVerilog/VerilogAMS to validate functionality before tape-out.
Designs high-performance memory systems for AI workloads using SystemVerilog RTL, synthesis, and PPA analysis to balance performance, power, and area from concept to silicon.
Design and implement timing-critical RTL blocks for memory/storage chips using SystemVerilog, focusing on latency, CDC, reset logic, and PVT-aware coding for advanced process nodes.
Leads hardware verification for AI-generated chip designs, ensuring rigorous validation of custom ASICs at tapeout stage using SystemVerilog, UVM, and Python, while collaborating with AI/ML and architecture teams to refine verification strategies and methodologies.
Designs and verifies ASIC IP for Qualcomm’s Snapdragon DSP/NPU, using UVM and SystemVerilog to accelerate AI and video workloads in connected devices.
Build AI-driven tools to automate RTL front-end design flows using agentic frameworks like LangChain/CrewAI, reducing manual effort in synthesis, STA, and verification.
Design Verification Engineer builds and runs ASIC/SoC verification environments using SystemVerilog and UVM to ensure chip designs meet specifications.
Video Codec Design Engineer, up to Staff Location: Taipei, Taipei City, Taiwan Department: ASICS Engineering Work Location: onsite Company: Qualcomm Semiconductor Limited Job Area: Engineering Group, Engineering Group…
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