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Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.
Designs and implements micro-architecture and RTL for AI chips, collaborating with cross-functional teams to deliver high-quality silicon solutions using SystemVerilog/VHDL and EDA tools.
Senior FPGA firmware developer designs, tests, and integrates custom VHDL firmware for torpedo sonar systems using Xilinx/Intel tools in a defense-focused engineering environment.
Senior FPGA firmware developer designs, tests, and integrates custom VHDL firmware for torpedo sonar arrays and embedded systems using Xilinx/Intel tools.
Senior firmware engineer designing FPGA-based control and video pipelines for advanced ophthalmic surgical systems in Erlangen, Germany, using VHDL/SystemVerilog and collaborating with hardware and software teams.
Principal Firmware Engineer (FPGA) designs and validates FPGA-based firmware for advanced ophthalmic surgical systems using VHDL/SystemVerilog and Xilinx/AMD Zynq UltraScale+ SoC in Erlangen, Germany.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Designs and verifies ASICs and FPGAs for high-speed optical transmission systems, implementing signal processing algorithms and collaborating with global teams to optimize power and performance.
Working student role in DRAM design, assisting engineers with IC schematics, simulations, and verification for high-performance memory solutions in Munich.
Design FPGA/ASIC digital systems for radar, electronic warfare, and communications using Verilog/VHDL, high-speed interfaces, and PCB tools while leading teams and collaborating across engineering and business functions.
Lead the physical design and implementation of high-performance processor chips from RTL to GDS in advanced nodes (5nm–2nm), managing global teams and sign-offs for timing, power, and DFM.
Lead the physical design and methodology for next-gen high-performance processor chips, managing RTL-to-GDS flows, timing, power, and sign-offs in advanced nodes (5nm–2nm) for server, 5G/6G, and networking applications.
Builds and tests Jasper, a formal-verification tool for clock-domain-crossing issues in chip design, using C++ and Unix workflows.
Lead a team enhancing Jasper, a formal verification tool for clock domain crossing in hardware design, using C++ and Unix in a fast-paced R&D environment.
Principal Analog Hardware Engineer designs and validates high-performance analog and mixed-signal circuits for next-generation test and measurement products in Santa Rosa, CA.
Design and verify FPGA modules for advanced systems, collaborating with hardware and software teams using VHDL/Verilog and Xilinx tools.
Principal FPGA engineer designing and verifying VHDL/Verilog modules for high-reliability electro-optical systems, using Xilinx tools and OSVVM/UVM testbenches.
Designs and implements FPGA-based digital logic for space systems like satellite command and control, using VHDL/Verilog and AMD/Microchip tools.
Design and implement real-time control systems for quantum networking hardware using FPGAs (Xilinx Zynq/Ultrascale) and embedded C/Rust, collaborating with physicists and engineers.
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