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Develop and maintain emulation models and infrastructure for Google’s custom silicon, scripting automation and debugging hardware flows to accelerate product development.
Design verification engineer building and debugging SystemVerilog/UVM testbenches for custom AI silicon IP and SoCs, ensuring functionally correct RTL before tape-out.
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on microarchitecture, RTL coding, and integration with AI/ML systems.
Develops a new automation tool for silicon CAD (chassis automation) to generate RTL, register definitions, and verification collateral from user requirements, collaborating with RTL, verification, and SoC teams using Python, structured schemas, and CI/CD pipelines.
Design and verify RTL hardware designs and SystemVerilog/UVM testbenches to train AI agents that automate chip design workflows.
Applications Engineer at ChipAgents guides enterprise customers through AI-driven chip design and verification workflows, integrating tools like Synopsys VCS and Cadence Xcelium to accelerate RTL development and verification.
Design and verify FPGAs for spacecraft test infrastructure, bridging hardware interfaces and enabling real-time functions like packet timestamping and command scheduling.
Designs high-performance PCIe Gen6/Gen7 switch ASIC IP using SystemVerilog, focusing on RTL implementation, timing closure, and architecture for next-gen connectivity solutions.
Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.
Senior embedded engineer designing and optimizing firmware/software for storage hardware, bridging hardware (FPGA) and software (Linux/RTOS) domains, and leading system integration from concept to production.
A Senior Product Security Engineer reviews and shapes security for ARM’s SoC and embedded firmware, focusing on threat modeling, code reviews (C/C++), secure boot, and hardware-backed protections like TrustZone. They collaborate cross-functionally to embed security into development and validate security assumptions through hands-on testing.
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the…
Designs and integrates Phase-Locked Loops (PLLs) and clocking IP for FPGA products on advanced process nodes, focusing on analog/mixed-signal blocks and system-level validation.
Verify next-gen x86 CPU cores by writing C++/SystemVerilog tests and checkers, debug RTL issues, and drive coverage closure in a hybrid Austin office.
Designs and implements test structures for high-performance AI ASICs, including scan insertion, ATPG, and post-silicon bring-up in cutting-edge CMOS processes.
Sr. Principal Digital Designer Location: Bangalore Time Type: Full time Job Description Role Summary We are seeking a Sr. Principal Digital Designer to lead the architecture, implementation, and integration of digital…
Sr. Principal Embedded Systems Security Architect Location: Shanghai (Pudong) Time Type: Full time Job Description Shape the Security of Tomorrow's Connected World At NXP, security is at the heart of everything we…
2027 Internship- Hardware Engineer (FPGA) Location: Austin, TX Department: Internships Virtu is an industry-leading financial technology firm that operates both proprietary trading and client-facing businesses in the…
Staff Engineer, Design Verification Engineering Location: India, Bangalore, RMZ Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that…
Staff Design Verification Engineer Location: India, Bangalore, RMZ Time Type: Full time Job Description About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the…
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