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Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
Build and maintain CI pipelines for ASIC front-end integration, automating EDA tools with Python/Tcl/Shell and managing Perforce streams for hardware silicon development.
Principal engineer designing and verifying PCIe/CXL IP subsystems in SystemVerilog for Marvell’s custom SoCs powering hyperscale cloud and AI data centers.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Design, simulate, and validate high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, I/O interfaces) for SoC timing products using Cadence tools and Verilog-A.
Principal firmware engineer designing DSP algorithms and embedded C/C++ code for ultra-low-jitter timing SoCs used in 5G, IoT, and autonomous vehicles.
Principal Design Engineer at Microchip Technology leading hardware/firmware co-development and pre/post-silicon verification using emulators and FPGA platforms for SoC devices.
Designs and verifies hardware security IP for SoCs, including cryptography, key management, and secure boot, using Verilog and scripting.
Engineer secure network services like PKI, load balancing, and DNS/DHCP for a government intelligence program, ensuring high availability and performance across classified DoD environments.
Designs and optimizes physical layouts for high-bandwidth memory (HBM) chips, focusing on floorplanning, power integrity, and signoff using Cadence/ Synopsys tools.
Designs and verifies FPGA-based digital circuits for automated trading systems, develops reusable IP, and integrates hardware with software stacks using SystemVerilog/Verilog/VHDL and C++.
Design and optimize FPGA systems to reduce latency and boost throughput for a proprietary trading firm, using SystemVerilog and automated verification.
Design high-speed VLSI circuits for next-gen CPUs, optimizing power, performance, and area while collaborating across teams to solve complex hardware challenges.
Validates FPGA-based power analysis tools by running tests, collecting data, and automating regression workflows using Python, TCL, and Vivado/Vitis.
Designs and optimizes ASIC physical layouts using Cadence/ Synopsys tools, closing timing and power while driving tapeout readiness in a fast-paced chip startup.
Lead backend ASIC implementation from RTL to tapeout, defining flows, optimizing PPA, and signing off DRC/LVS for advanced-node chips.
Validate custom CPU silicon for Google’s consumer products, executing test procedures and debugging failures with hardware, software, and manufacturing teams.
Designs, implements, and tests FPGA firmware for high-speed electric compressors used in aerospace and heat pumps, using VHDL and Xilinx tools.
With our groundbreaking satellite 5G constellation, OQ Technology is a global leader in IoT communication connectivity and associated services. We are a venture capital-backed company with a successful track record of…
Develops FPGA-based digital signal processing and communication protocol modules in Verilog/SystemVerilog, tests and integrates them with hardware, and participates in lab and system testing.
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