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Systems Design Engineer, Digital Signal Processing _corporate_fare_ Google _place_ Sunnyvale, CA, USA Advanced Experience owning outcomes and decision making, solving ambiguous problems and influencing stakeholders;…
Sr Principal Design Engineer Location: SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Join our North America…
Sr Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Joining our Palladium…
Intern designs FPGA/ASIC solutions for ultra-low-latency trading systems, writing and verifying RTL in SystemVerilog and bringing designs up on live hardware.
Design and verify custom silicon chips for next-generation data storage hardware, using RTL, Verilog/SystemVerilog, and digital logic while collaborating with cross-functional engineering teams.
Design and verify custom silicon and hardware for next-generation data storage devices, collaborating across ASIC, firmware, and systems engineering teams using RTL, Verilog, and embedded C/C++.
Build AI-powered tools to automate and enhance semiconductor verification workflows, using Python, LLMs, and cloud DevOps for faster, smarter hardware development.
An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
Experienced FPGA Developer Location: Rancho Santa Margarita, CA, us Company Description CS Group USA, a subsidiary of CS Group, is a key player in the development and certification of safety-critical systems in the…
Principal Engineer leading pre-silicon verification of complex digital SoCs, AI/ML accelerators, and high-speed peripherals using UVM, formal methods, and emulation for edge computing products.
Lead FPGA design and architecture for defense electronics using VHDL, targeting Xilinx/Altera/Microsemi devices, and verify with constrained-random testing.
Designs and integrates RTL blocks into SoCs, runs linting, CDC/RDC checks, synthesis, and gate-level simulations using tools like NCSim and VCS.
Designs and implements ASIC/SoC RTL (Verilog/SystemVerilog) for high-performance SSD controllers, collaborating with verification, validation, and firmware teams to deliver next-gen enterprise and AI data center storage solutions.
What you’ll do Act as the in-house electrical lead for Midjourney Medical: own the electrical architecture of the scanner and the technical direction for all board-level design. Own complex board design end-to-end:…
Senior Hardware Design Engineer Department: US Jobs Employment Type: Permanent Location: West Coast, United States, Hybrid We are looking for multiple Senior Design Engineers who will work on revolutionary technology…
Designs and integrates hardware components into Apple’s next-gen SoC, writing and merging RTL code, managing IP blocks, and ensuring timing closure with industry-standard tools.
Designs and verifies custom silicon for Google's TPU AI accelerators, focusing on SoC-level RTL, architecture, and integration within AI/ML systems.
Design verification engineer at AMD, building and running tests to validate next-generation x86 CPU cores using C++, Verilog, and SystemVerilog.
Build AI tools that speed up AMD’s hardware and software engineering workflows, such as design optimization, verification, and debugging, by turning manual processes into AI-assisted systems.
Lead a team designing secure silicon IP blocks for chips, using Verilog/VHDL, cryptography, and formal verification in a hybrid office setting.
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