Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Develops FPGA-based digital signal processing and communication protocol modules in Verilog/SystemVerilog, tests and integrates them with hardware, and participates in lab and system testing.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/VHDL and ASIC flows.
Design and implement Verilog RTL for SoC blocks, integrate IPs, and optimize performance through synthesis, timing closure, and power reduction in a semiconductor R&D team.
Lead the physical design and tapeout of energy-efficient AI/ML SoCs, integrating blocks, timing, power, and signal integrity to deliver GDS-ready chips using advanced finfet nodes.
Design-for-Test engineer implements chip-level testability features (scan, MBIST, ATPG) and debugs DFT-related timing/power issues to ensure silicon test success.
Design Verification Engineer at Texas Instruments in Knoxville builds and runs test benches to verify analog and mixed-signal ICs, ensuring first-pass silicon success for industrial, automotive, and consumer applications.
Designs high-performance analog/mixed-signal circuits (PLLs, ADCs/DACs, RFIC) using Cadence Virtuoso, Spectre, and Mentor Calibre, with multi-node process experience from 28nm to 7nm.
Job Overview: This opening is for a memory layout designer in our PHYSICAL IP – MEMORY group in Noida. We work on innovative memory architectures in pioneering technology nodes to enable the best Arm Systems in all the…
Designs and verifies high-performance FPGA and SoC solutions in VHDL/Verilog, integrating IP and optimizing timing for mission-critical applications.
Lead validation of Cadence’s Innovus EDA tool, focusing on place-and-route features, writing Perl/Tcl/Python test utilities, and improving regression coverage.
Job Description Meet the Team Join the Package Design Team at Cisco Silicon One in Armenia, a group leading the way in developing Cisco's groundbreaking silicon solutions for next-generation networking. As a…
Design Verification Engineer builds and runs test environments for complex ASIC and mixed-signal IP using SystemVerilog/UVM, coverage analysis, and debug to ensure correctness before tape-out.
Designs and implements ASIC physical design flows (RTL-to-GDS) using EDA tools and AI-assisted methodologies to optimize PPA and timing for tape-out.
Designs IO pad rings, bump patterns, and connectivity for advanced SoC storage/memory controllers using EDA tools and scripting.
Designs and optimizes advanced ASICs for Cisco’s networking hardware, using EDA tools like Innovus and Tempus to perform RTL-to-GDSII flows, timing closure, and power integrity analysis.
Designs and validates high-speed analog and mixed-signal IP blocks (PLLs, ADCs, DACs, filters) for multi-GHz timing products using Cadence tools and Verilog-A modeling.
Обязанности: Разработка и отладка проектов для ПЛИС. Документирование разработанных проектов. Требования: Высшее (техническое) образование, предпочтительно-в области радиотехники. Опыт работы от 3-х лет в разработке и…
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Design and implement timing-critical RTL blocks for memory/storage chips using SystemVerilog, focusing on latency, CDC, reset logic, and PVT-aware coding for advanced process nodes.
Develops embedded firmware and audio algorithms for Google Pixel earbuds, integrating signal processing and acoustics to enhance hearing and speech features.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
