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Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog and collaborating with verification and physical implementation teams.
Designs and implements FPGAs and ASICs for SpaceX's Starlink network using Verilog/SystemVerilog, collaborating across teams to enhance satellite and ground infrastructure connectivity.
Designs and verifies next-generation FPGAs and ASICs for SpaceX’s Starshield national security programs, using Verilog/SystemVerilog, EDA tools, and collaborating with verification and physical implementation teams.
Designs and implements high-performance ASICs in Verilog/SystemVerilog for SpaceX’s Starlink network, collaborating with cross-functional teams to deliver space-grade silicon for global connectivity.
Designs and optimizes advanced ASIC/SOC chips for SpaceX's Starlink satellites and ground systems, focusing on physical implementation, timing closure, and verification using EDA tools.
Designs and implements advanced ASIC/SOC chips for SpaceX’s Starlink network, focusing on physical design flows, timing closure, and signoff checks to enable global satellite internet connectivity.
Designs, scales, and automates high-performance computing infrastructure for SpaceX's Starlink silicon engineering, enabling faster chip design iterations and simulations.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, using SystemVerilog, UVM, and Python to ensure reliable satellite and ground infrastructure connectivity.
Design Verification Engineer at SpaceX developing and testing next-generation ASICs for Starlink's satellite and ground infrastructure using SystemVerilog, UVM, and Python.
Designs and integrates RF and analog integrated circuits for space-grade hardware, focusing on layout, parasitic minimization, and tape-out for national security projects.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring satellite and ground infrastructure connectivity through pre- and post-silicon validation.
Designs and verifies next-generation ASICs for SpaceX’s Starlink network, ensuring chips meet performance and reliability needs for global satellite and ground infrastructure.
Designs and integrates RF and analog layouts for advanced satellite and national security ICs, using EDA tools and scripting to meet space-grade requirements.
Designs and integrates RF and analog layouts for advanced satellite and ground infrastructure chips, ensuring performance and manufacturability while collaborating with cross-functional engineering teams.
Designs and optimizes RF and analog integrated circuit layouts for satellite and ground infrastructure, ensuring performance and manufacturability in advanced nodes.
Manage complex ASIC/silicon projects end-to-end — planning, cross-functional coordination across architecture/RTL/DV/physical design/manufacturing, vendor and IP partner management, and risk mitigation — using standard project-management tools.
About Attotude AttoTude is at the forefront of revolutionizing data centers through advanced interconnect technology based on wired THz transceivers. By adapting the fiber from photonics and advancing today's ASICs…
Lead a team to verify system-on-chip designs for memory/storage solutions, ensuring first-pass silicon success and collaborating with architecture and validation teams.
Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology…
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