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We are looking for a Senior Engineer (FPGA) to join a Radio & Communications division and play a key role in the design, architecture, and development of advanced communication systems. This role focuses on…
The Wireless Systems Engineer will develop and implement algorithms for satellite-to-Bluetooth connectivity, focusing on system-level design, modeling, and simulation. The role involves cross-functional collaboration to build a global IoT network using off-the-shelf Bluetooth chips.
Designs and verifies digital controllers for high-performance ADC/DAC data converters: Verilog RTL coding, behavioral modeling, and testbenches, plus support for synthesis, timing closure, and place-and-route in advanced CMOS. Requires 2+ years in digital/mixed-signal IC development; based in Bengaluru.
Leads high-speed evaluation board development end to end for Omni Design's semiconductor IP — spec, schematic capture, PCB layout, bring-up, and bench debug. Lab-heavy role: RF signal paths up to 64 GHz, ADC/DAC characterization, BERT/oscilloscope testing, S-parameter validation, and FPGA/MCU integration.
Senior engineer doing RTL and FPGA design and verification of digital blocks for Omni Design's next-generation wireless chips targeting automotive and space applications. Day to day: analyzing power/performance/area tradeoffs, implementing test strategy and BIST, validating on FPGA, and leading silicon design with Verilog/SystemVerilog, UVM, C/C++ and scripting.
Senior Digital Design Engineer at Omni Design Technologies working on the digital datapath and controllers of high-performance ADC/DAC data converters. Day-to-day covers RTL design and verification, behavioral modeling, synthesis, timing closure, and P&R support in advanced CMOS, using Verilog/SystemVerilog and Cadence tools like Genus, Tempus and Innovus.
Senior engineer designing and verifying the digital controller for high-performance ADC/DAC data converters: writing Verilog RTL and behavioral models, building testbenches, and running synthesis, constraints, and place-and-route flows in advanced CMOS.
Senior technical leader who owns system architecture for next-generation multi-antenna and software-defined-radio (SDR) wireless platforms: building MATLAB/Python signal-chain models, setting SNR/phase-noise and error budgets, writing block-level specs for digital and mixed-signal teams, and leading technical engagements with strategic customers. Applied to semiconductor IP for 5G, radar, LiDAR, a
Leads and manages the digital engineering team at Omni Design Technologies, driving development of mixed-signal SoCs for automotive and space applications — from RTL design, integration, and verification through timing closure and silicon validation. Core tools: Verilog/SystemVerilog, UVM, Cadence/Synopsys flows, and FPGA emulation.
Lead engineer at Cadence (posted under SECURE IC) in Noida who independently owns the design, development, and delivery of Formal Verification IPs — writing Verilog design models, SystemVerilog Assertions, and RTL for protocols like AXI, CHI, PCIe, and CXL, with Python/Tcl automation and EDA formal-verification tools.
Designs and implements FPGA code for Kepler's satellite digital payloads — either DSP algorithms for software-defined radios or embedded systems interfacing with processors — across the full design flow (simulation, synthesis, place & route, timing closure, hardware testing) using Xilinx FPGAs and HDLs like Verilog/SystemVerilog.
An AMS Firmware Engineer at Apple specifies, designs, verifies, and helps bring up the digital side of advanced custom mixed-signal circuits that connect Apple products to the physical world. Core work centers on RTL design with Verilog/SystemVerilog and front-end tools like simulators, linters, and CDC checkers.
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering ( SCHIE ) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Designs, implements, and validates FPGA-based digital microarchitectures using Verilog/SystemVerilog for quantum computing systems in Palo Alto.
Lead front-end (RTL) design engineer on the team developing next generations of Cerebras' Wafer Scale Engine AI chip. Day to day: owning functional specs, micro-architecture, RTL development and synthesis, coordinating with external ASIC vendors and verification/PD/software teams, and debugging silicon during bring-up. Core skills: RTL design, chip/IP integration, networking protocols, Python/TCL.
Design verification engineer at Cerebras Systems, defining verification strategies and building SystemVerilog/UVM testbenches, coverage plans and regression infrastructure for its wafer-scale AI chip, and debugging across simulation, emulation, and silicon bring-up. On-site in Sunnyvale, CA; requires 14+ years of DV experience. Pays $250k-$300k base.
Design Verification Engineer who builds verification strategies, UVM/SystemVerilog testbenches, and coverage plans for Cerebras' wafer-scale AI chips, running regressions and debugging across simulation, emulation, and silicon bring-up. Requires 3+ years of DV experience plus Python/Perl scripting; onsite in Sunnyvale, CA.
Senior Physical Design Engineer at SiFive (RISC-V semiconductor company) in Bengaluru, owning end-to-end RTL-to-GDS implementation — synthesis, floorplanning, place & route, and signoff — for next-gen compute IPs, co-optimizing with RTL/architecture teams to hit power, performance, and area targets using Synopsys and Cadence tools.
Principal-level (PMTS) digital design engineer at semiconductor foundry GlobalFoundries, leading microarchitecture and RTL design of high-performance CPU cores and SoC subsystems from concept through silicon. Day to day: Verilog/SystemVerilog RTL, PPA optimization, design reviews, mentoring, and collaboration with verification, physical design, DFT, and bring-up teams.
Lead embedded software architect/developer for FPGA SoC and CPU SoC image processing and control in battery-powered night vision goggles, wideband RF signal processing, and synthetic aperture radar systems. Core tech: Xilinx Vitis/Vivado, embedded Linux/Yocto, CUDA on NVIDIA Jetson, and real-time Arm multicore development.
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