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Valeo is a tech global company, designing breakthrough solutions to reinvent the mobility. We are an automotive supplier partner to automakers and new mobility actors worldwide. Our vision? Invent a greener and more…
Date Posted: 2026-10-23

 Country: United States of America

 Location: US-CT-EAST HARTFORD-J ~ 400 Main St ~ BLDG J

 Position Role Type: Onsite

 U.S.…
About GlobalFoundries GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology…
Monolithic Power Systems, Inc. (MPS) is one of the fastest growing companies in the Semiconductor industry. We are worldwide technical leaders in Integrated Power Semiconductors and Systems Power delivery…
About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, AI,…
Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure‑play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than…
Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
Overview Microsoft is the world’s center of expertise on topological quantum computing. We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure…
Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication…
Front-end ASIC design engineer responsible for RTL implementation and verification of complex logic blocks, supporting synthesis, DFT, STA, tape-outs, and chip bring-up at a high-speed interconnect semiconductor company. Core tech includes Verilog/SystemVerilog, Serdes, Ethernet, UVM, and timing analysis.
Make the Holidays Brighter with TCL and Help Shoppers Find Their Perfect Entertainment Upgrade! Looking for a seasonal role that blends your passion for technology and customer service? Join ActionLink as a Seasonal…
Senior ASIC Design Engineer Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products…
Senior Foundation IP design expert at Alibaba's DAMO Academy: designs and delivers full-custom circuit IP (standard cells, SRAM, IO, analog/mixed-signal blocks like LDO and PVT sensors) for high-performance computing chips, covering PDK interpretation, PPA optimization, library delivery (LEF/GDS/Liberty), and sign-off verification with SPICE, Calibre DRC/LVS, and PVT corners.
职位描述 参与芯片整体Floorplan、Partition、STA等方案制定。 负责芯片整体Partition划分及Harden代码的具体设计与实现。 负责芯片整体设计SDC约束与预综合交付，协助中后端团队实现PPA优化。 根据中后端反馈（时序、功耗、面积等瓶颈），指导前端微架构和设计修改。 职位要求 电子、计算机等相关专业，本科及以上学历，8年以上SoC前端设计或顶层集成经验。…
1.与CPU设计者密切合作，进行关键时序路径的分析与逻辑电路优化； 2.前后端协同设计，持续提升CPU PPA性能指标； 3.CPU Core的物理设计与交付，达到产品指标要求； 4.CPU 集成实现工程师（中端）综合实现 1. 具有CPU/GPU/AI Core物理设计及实现经验优先； 2. 与CPU设计者密切合作，进行逻辑优化，持续提升CPU PPA指标； 3.…
1. 负责基础工艺IP（Foundation IP）设计与交付，包括Standard Cell、SRAM、IO及其他数模混合 IP（如CML、LDO、PVT Sensor等） 2. 深入理解并解读Foundry PDK、工艺规则与特性，与工艺厂保持紧密技术协作，分析并解决与工艺波动、可靠性（EM/IR-drop/Aging 等）相关的设计挑战 3. 针对产品目标与工艺特性进行定制化电路设计，优化…
1. 负责top floorplan，电源网络，partition， 时钟树， IO assignment 等规划 2. 建立后端sign off spec，signoff 策略 和signoff checklist，包括STA, EM/IR, PV 等 3. 负责先进工艺中后端流程开发 4. 负责关键ip的ppa 优化 5. 与前端构架深入合作，保证构架设计可实现性与ppa 优化 1.…
● 负责SOC、subsystem 逻辑综合、DFT merge、形式验证、STA signoff等工作。 ● 和前后端团队合作，完成芯片设计过程中 clock/reset方案，low power和power domain划分方案，时序收敛等工作。 ● 熟悉SDC、timing check、VCLP/CLP check，成为流片前timing质量把关人。 ● 电子、计算机等相关专业，硕士及以上学历，3年及以上SoC逻辑综合经验。 ●…
DAMO Academy (Alibaba Group) is hiring a chip physical-design (implementation/backend) engineer/expert for its RISC-V ecosystem program. Day-to-day work covers full-chip floorplanning, physical synthesis, place & route, PPA optimization, timing/IR/EM/DRC/LVS sign-off, and backend flow automation using EDA tools plus Tcl/Perl/Python scripting.
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