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Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and…
We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design,…
About Us At onsemi , we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in creating a safer, cleaner,…
Intern in Digital IC Design About Us At onsemi , we help improve lives through silicon solutions every day. Our intelligent power and sensing technologies solve the world’s most complex challenges and lead the way in…
Principal HW/SW Co-Design engineer at NXP in Catania: a technical lead bridging hardware and software teams to build high-quality low-level MCU device drivers, verified in RTL simulation and emulation before tapeout and delivered via SDK. Core tech: C/C++/Assembly, ARM subsystems, embedded RTOS, RTL bring-up, Git/JIRA/Confluence.
Senior physical design role on NXP's new Catania MCU team, implementing complex high-performance chips day to day: floorplanning, power grid, place and route, clock tree synthesis, static timing closure, power/signal integrity, and physical verification (DRC/LVS) with EDA tools like Cadence Innovus, Synopsys ICC2/PrimeTime, and Ansys RedHawk, plus mentoring junior engineers.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Job Overview: As a part of Arm's Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power,…
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible…
Senior RTL design engineer at AMD in Bangalore who develops and integrates in-house and vendor IPs, subsystems, and SoC designs, ensuring quality via static checks (LINT, CDC, RDC, CLP/VCLP), owning constraints like SDC/UPF, and driving timing closure and verification. Core skills: RTL coding, VLSI fundamentals, and protocols like PCIe and AMBA.
About MIPS @ GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired…
Job Details: Job Description: About the Role Altera is seeking a Principal High-Speed Interface / Silicon Design Engineer to lead the architecture, design, integration, and verification of advanced high-speed interface…
Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Lead verification of safety-critical FPGAs for Radiant's nuclear microreactor control, instrumentation, and communication systems — building SystemVerilog/UVM testbenches, driving coverage closure, and collaborating with RTL, hardware, and embedded software teams. Onsite in El Segundo, CA.
FPGA/ASIC engineer at Virtu Financial in Dublin designing and verifying RTL for low-latency trading applications on the firm's proprietary trading platform, owning designs from specification through verification to live production deployment using SystemVerilog/VHDL, cocotb, and Xilinx/AMD, Synopsys, and Cadence toolchains.
Senior silicon design engineer on AMD's Radeon Technologies Group in San Jose (hybrid), implementing and verifying DFT architecture: scan insertion, ATPG pattern generation and gate-level simulation, test coverage/cost analysis, and post-silicon bring-up support using tools like Tetramax, Testkompress, and VCS.
At AMD's San Jose office (hybrid), a Sr. Staff ASIC Design Engineer joins the front-end design/integration team for next-generation graphics and compute silicon, focusing on DFT: scan insertion, ATPG pattern generation, gate-level simulation verification, test-cost analysis, and post-silicon bring-up. Tooling includes VCS, TetraMAX/DFTMAX, TestKompress, Perl/Shell, and Verilog RTL.
Meet the Team We are part of the Hardware Platform Group, with our team specializing in FPGA development. Our work spans both sophisticated data-path and challenging control-path FPGAs. The design process includes…
Alternate Job Titles Digital Verification Senior Staff Engineer Mixed-Signal PHY Verification Lead ASIC Verification Sr Staff Engineer RTL/GLS Verification Senior Staff Engineer High-Speed Interface Verification Senior…
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