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Lead a team designing secure silicon IP blocks for chips, using Verilog/VHDL, cryptography, and formal verification in a hybrid office setting.
FPGA Prototyping Staff Applications Engineer Location: Bengaluru, India We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We…
Front-End & Back-End SoC Engineering, Principal Engineer Location: Munich, Germany We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered…
SOC Engineering, Staff Engineer - RTL Design Location: Noida, India Job Title: RTL Design Engineer, Staff Level - SoC Design We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling…
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC solutions for edge connectivity applications.
Lead architecture and RTL design for Automotive Ethernet PHY subsystems, implementing PCS pipelines, safety mechanisms, and ISO 26262-compliant logic in Verilog/SystemVerilog.
Principal Engineer in Marvell’s Design Verification team, building and running testbenches to verify high-speed storage IP like read channels and cryptographic engines using SystemVerilog/UVM and EDA tools.
Design verification engineer building and running testbenches for high-speed storage IP (HDD/SSD) using SystemVerilog/UVM and collaborating with SoC teams to debug complex digital designs.
Architects and implements pre-silicon verification strategies using UVM or formal methods, builds testbenches, and integrates block-level tests into chip-level environments for Intel hardware designs.
Develops and maintains safety-critical embedded flight software in C/C++ for spacecraft avionics, integrating with microcontrollers and real-time systems to support hypersonic reentry operations.
- Bachelor's degree or above in computer science, electrical engineering, or related field - - 3+ years of hands-on post-silicon validation or system validation engineering experience - - Strong programming skills…
Lead ASIC verification for Google Cloud hardware, owning outcomes, decisions, and stakeholder alignment using SystemVerilog and UVM.
Designs and implements high-speed FPGA-based trading systems to accelerate network infrastructure and trading components, working closely with traders and software engineers.
Designs and implements low-latency hardware trading systems using FPGAs and ASICs, collaborating with traders and software engineers to solve complex financial market problems.
Designs and optimizes FPGA-based hardware for ultra-low-latency trading systems, coding in VHDL and collaborating with software teams to enhance market-making infrastructure.
Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.
Designs and implements micro-architecture and RTL for AI chips, collaborating with cross-functional teams to deliver high-quality silicon solutions using SystemVerilog/VHDL and EDA tools.
Designs and integrates advanced semiconductor logic for AI chips in Bengaluru, using SystemVerilog, Python, and digital design flows to deliver RTL and microarchitecture for Graphcore’s silicon.
CAD RTL/DV Infrastructure Engineer, Sr Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
CAD RTL/DV Infrastructure Engineer, Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
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