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Design and implement timing-critical RTL blocks for memory/storage chips using SystemVerilog, focusing on latency, CDC, reset logic, and PVT-aware coding for advanced process nodes.
Develops embedded firmware and audio algorithms for Google Pixel earbuds, integrating signal processing and acoustics to enhance hearing and speech features.
Designs next-gen WLAN hardware at the RTL/IP level, focusing on logic synthesis, timing constraints, and low-power optimization for 6nm+ processes using tools like Genus, Primetime, and Tcl scripting.
Implementation Timing / STA Design Engineer Location: San Diego, California, United States of America Department: ASICS Engineering Work Location: onsite Company: Qualcomm Technologies, Inc. Job Area: Engineering…
Design verification engineer building UVM testbenches for high-speed interconnects (PCIe, CXL, AXI) to ensure ASIC/subsystem correctness before tape-out.
Lead a team to perform Static Timing Analysis (STA) on Google’s custom silicon SoCs, ensuring timing closure and low power for AI accelerators while collaborating with architecture and physical design teams.
Designs and executes test plans for GPON/XGS-PON broadband hardware, validating L2/L3 protocols and OLT/ONT devices using Python automation and tools like Spirent/Ixia.
Senior Engineer plans, coordinates, and executes IC package design programs from feasibility through manufacturing, driving clarity and reducing execution risk while collaborating with cross-functional teams.
Designs and optimizes digital ASIC layouts from netlist to GDSII using EDA tools like Synopsys ICC2 or Cadence Innovus, scripting in Python/TCL, and exploring AI-assisted flows for advanced process nodes (TSMC N5/N4P/N3).
Senior Physical Design Engineer at Qualcomm leading floorplanning, placement, and timing closure for high-speed digital blocks on advanced nodes (TSMC N5/N4P/N3) using Synopsys ICC2, Cadence Innovus, and AI-assisted EDA flows.
Designs and optimizes CPU physical layouts using Place & Route tools (FC/Innovus), STA (Primetime/Tempus), and UPF/CPF for low-power, high-speed ASICs.
Develop and maintain emulation models and infrastructure for Google’s custom silicon, scripting automation and debugging hardware flows to accelerate product development.
Designs and troubleshoots hard-disk-drive systems, analyzing failures in electromechanical, firmware, and media components to improve yield and quality.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Senior Physical Design Architect at Altera to implement FPGA/SoC backend flows from RTL to GDSII, optimizing performance, power, and area while improving PD automation.
Applications Engineer at ChipAgents guides enterprise customers through AI-driven chip design and verification workflows, integrating tools like Synopsys VCS and Cadence Xcelium to accelerate RTL development and verification.
Designs and verifies chip-level layout for high-performance memory-interface chips using Cadence Virtuoso and Calibre in 22nm–7nm nodes.
Design and verify FPGAs for spacecraft test infrastructure, bridging hardware interfaces and enabling real-time functions like packet timestamping and command scheduling.
Principal Engineer designs and runs pre-silicon verification for DDR, HBM, and GDDR memory controller IP using SystemVerilog and UVM, with coverage-driven test suites and regression monitoring.
Lead verification engineer building testbenches and coverage plans for PCIe/CXL controller IP using SystemVerilog/UVM and scripting in Python/TCL.
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