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Security RTL Design Engineer-Sr Lead/Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Senior IP Micro-architect (RTL) - Staff/Sr Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
DSP / NPU Staff Design Verification Engineer Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Lead the design of a next-generation edge SoC for a stealth startup, defining microarchitecture, driving PPA tradeoffs, and integrating high-performance IP to power a custom computing platform.
Design verification engineer leading pre-silicon verification for complex SoCs, using UVM, SystemVerilog, and formal methods to ensure correctness of AI/ML accelerators, processors, and interconnects.
Senior engineer verifying FPGA-based designs for NVIDIA’s Holoscan edge-compute platform, using SystemVerilog/UVM and collaborating with architecture teams to validate real-time AI and connectivity features.
Senior firmware engineer designing FPGA-based control and video pipelines for advanced ophthalmic surgical systems in Erlangen, Germany, using VHDL/SystemVerilog and collaborating with hardware and software teams.
Principal Firmware Engineer (FPGA) designs and validates FPGA-based firmware for advanced ophthalmic surgical systems using VHDL/SystemVerilog and Xilinx/AMD Zynq UltraScale+ SoC in Erlangen, Germany.
Integrate hardware security IP (RoT, crypto engines, HSMs) into AI-focused SoCs, define secure boot/attestation, and architect protections against physical/side-channel attacks for data-center hardware.
Design and verify ASIC/SoC hardware in Verilog/SystemVerilog, then evaluate and improve how AI models understand chip engineering tasks.
Design and prototype next-gen AI hardware using FPGAs, focusing on SoC emulation, high-speed interfaces like PCIe/LPDDR, and bring-up for analog compute-in-memory chips.
Design and implement real-time control systems for quantum networking hardware using FPGAs (Xilinx Zynq/Ultrascale) and embedded C/Rust, collaborating with physicists and engineers.
FPGA Lead/Architect/Implementor Location: Denmark - Kongens Lyngby Time Type: Full time Job Description Be visionary Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that…
Designs and integrates Phase-Locked Loops (PLLs) and clocking solutions for AMD's FPGA products, focusing on advanced process nodes and system-level validation.
Mixed-Signal Design Verification Engineer | Custom Location: Dallas, TX, United States We are seeking a talented Mixed-Signal Design Verification Engineer with experience in verifying high-speed wireline communications…
Designs and develops cryogenic CMOS analog circuits for quantum computing control systems, collaborating with hardware and physics teams to build scalable quantum platforms.
Validate and bring up custom AI silicon from first power-on through production, testing boot, memory, interconnects, and high-speed interfaces while debugging cross-functional failures.
Designs and verifies custom silicon for Google’s TPU AI accelerators, focusing on control subsystems and SoC integration within AI/ML-driven systems.
Design and verify digital ASIC front-end architectures for radiation monitoring systems using open-source EDA flows, collaborating with analogue and verification teams.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
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