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Develop low-level diagnostics and system software for an AI inference platform, including firmware, drivers, and Linux kernel modules, while collaborating with hardware teams on bring-up and optimization.
Design and optimize high-performance processor chips using advanced EDA tools, focusing on synthesis, place-and-route, timing closure, and ECOs for server, 5G/6G, and networking applications.
Designs and optimizes VHDL/Verilog hardware components for networking systems (SmartNICs, optical switches), writes test cases in Python, performs timing analysis, and collaborates with software/networking teams on system-level debugging.
Develop and optimize C++ algorithms for IR drop, timing, and physical design to improve chip performance and power efficiency in advanced VLSI flows.
Senior engineer designing data pipelines and applying AI/ML to analyze and optimize semiconductor test methodologies for NVIDIA's next-gen chips.
Develop and optimize FPGA placement algorithms to improve timing, power efficiency, and design quality within Altera’s compiler toolchain.
Role Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the…
Principal Logic Design Engineer Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Principal Logic Design Engineer to join our…
Lead the physical design of high-performance chip IP blocks using Cadence Innovus, focusing on floorplanning, place-and-route, timing closure, and manufacturability sign-off.
A Salesforce developer builds, configures, and maintains Salesforce CRM solutions (e.g., Sales, Service Cloud) using Apex, Lightning Web Components (LWC), and Flow, ensuring seamless integration for sales, marketing, and customer service teams.
Lead a team designing and automating Design-for-Test (DFT) features for complex ASICs, GPUs, and APUs using Perl, Python, TCL, and AI/ML tools.
Design Verification Engineer at AMD builds and maintains tests to verify complex processor IP, debug failures, and collaborate with RTL and firmware teams to ensure high-quality silicon designs.
Designs and implements DFT/DFD features for AMD’s ASICs (APUs, GPUs, game consoles) while automating workflows via Python/Perl/TCL scripts and debugging CAD/IP regressions.
Design engineer optimizing RTL-to-GDS flows for AMD’s chip projects, scripting tool flows in TCL/Python, and collaborating with global teams on synthesis, place-and-route, and physical signoff.
Design and tape out advanced ASIC/SoC testchips using RTL-to-GDS flows, timing closure, and physical signoff for leading-edge process nodes.
Build AI-driven automation and EDA workflows to accelerate advanced semiconductor package and interposer design, reducing manual effort and improving signal integrity and power delivery.
Senior Physical Design Engineer implements high-performance ASICs in 3nm nodes, driving timing closure, power integrity, and physical verification for AI data-center photonics chips.
Designs and validates test solutions for digital, analog, and photonic logic in AI-focused chip platforms, using DFT methodologies like ATPG and boundary scan to ensure silicon bring-up and product readiness.
Designs and implements test structures for high-performance AI ASICs, including scan insertion, ATPG, and post-silicon bring-up in cutting-edge CMOS processes.
Associate Principal Engineer - Senior C++ Developer Location: Washington County, Pennsylvania, us Company Description We are a Digital Product Engineering company that is scaling in a big way! We build products,…
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