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Leads a team of developers to build and maintain AI training datasets, ensuring quality and efficiency while mentoring staff and reporting progress to clients.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And…
Architect and lead formal verification strategies for complex ASIC designs, guiding teams to ensure silicon quality for next-gen processors and I/O technologies.
Designs and executes SoC verification for AMD’s next-gen ASIC and FPGA chips, writing testbenches in SystemVerilog/UVM and debugging failures to ensure bug-free silicon.
Build and deploy AI agents that automate silicon IP design using RAG, agentic workflows, and EDA tool integration to accelerate spec-to-netlist pipelines.
Lead verification of AMD’s IOHUB subsystem, defining test plans and collaborating with global teams to ensure high-performance interconnect IP meets design specs.
Design verification engineer building PCIe interconnect IP testbenches using UVM/SystemVerilog to validate high-performance ASIC features for AMD’s GPUs, APUs, servers, and consoles.
Design verification engineer at AMD, building and automating tests for next-gen network processors and SmartNICs using UVM, SystemVerilog, and AI-assisted workflows.
Design Verification Engineer at AMD builds and runs testbenches in SystemVerilog/UVM to validate DDR5/LPDDR5 memory interfaces and DFI protocols for server products.
Lead verification of DDR5/LPDDR5 memory interfaces for server products using SystemVerilog, UVM, and formal methods; mentor engineers and collaborate with hardware, firmware, and software teams.
Design Verification Engineer at AMD building and running testbenches for DDR5/LPDDR5 memory interfaces using SystemVerilog, UVM, and C/C++ to validate server memory products.
Lead a team designing and integrating RTL for SoC subsystems, ensuring first-pass silicon success through collaboration with architecture, verification, and physical design teams.
Lead MTS Logic Design Location: Vught, UNAVAILABLE, NL Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional Lead Member of Technical Staff Logic Design…
Principal Engineer designs and verifies memory controller IP for DDR/HBM/GDDR DRAM, building SystemVerilog testbenches and coverage-driven regression suites.
Lead RTL design for IP subsystems, integrating AMD and third-party IPs, ensuring first-pass silicon success through quality checks and collaboration with verification and physical design teams.
Design Verification Engineer for PCIe and CXL controller IP, building testbenches and coverage plans in SystemVerilog/UVM to validate new controller features before tape-out.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/SystemVerilog, collaborating with architects and software teams to meet security and quality standards.
Develops automation tools and flows for front-end chip design verification, synthesis, and package generation using SystemVerilog, Python, and EDA tools.
Principal PCIe Logic Design Location: Hillsboro, OR, US Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our…
PE Logic Design Location: Bangalore, KA, IN Employment Type: OTHER Overview Rambus, a premier chip and silicon IP provider, is seeking to hire a motivated full-time Principal Design engineer to join our PCIe IP design…
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