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An intern in AMD’s Singapore design center works on cutting-edge IC design tasks like analog/digital design, verification, or post-silicon validation using EDA tools such as Cadence and Synopsys, contributing to high-speed SerDes and AI-related chips.
3DExperience Enovia Technical Technical Consultant Location: Bengaluru, Karnataka, in Company Description About Sopra Steria Sopra Steria, a major Tech player in Europe with 51,000 employees in nearly 30 countries, is…
Hardware Engineer specializing in RTL/PD, optimizing designs from microarchitecture to tapeout for AI-native ASICs at Normal Computing, a deep-tech semiconductor startup.
AppLogic Networks powers the networks behind AI and the critical applications people rely on every day. We help network owners service providers and Enterprises understand how applications perform, how users experience…
Senior architect designs and leads 3DEXPERIENCE/ENOVIA PLM implementations, defining scalable solutions, security models, and integrations with enterprise systems like SAP.
Senior Engineer - Low Power Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow with us About this Opportunity Join Ericsson's cutting-edge journey to shape the…
Senior Engineer - Physical Design Location: Bangalore,Karnataka,India Department: 76 Product Development Work Location: onsite Grow with us About this Opportunity Join Ericsson's cutting-edge journey to shape the…
Design verification engineer at Apple’s Nabern office, verifying next-gen power-management ICs using mixed-signal verification flows, hardware description languages, and analog behavioral models to ensure high-quality silicon tape-outs.
Principal Engineer leading pre-silicon verification of complex digital SoCs, AI/ML accelerators, and high-speed peripherals using UVM, formal methods, and emulation for edge computing products.
Designs and implements high-performance memory compilers and RTL blocks for custom SoCs, collaborating with architecture, verification, and physical design teams to deliver silicon-ready IP.
Designs low-power wireless System-on-Chip solutions, writing RTL code and guiding the SoC through synthesis, timing analysis, and tape-out while collaborating with global teams.
Designs and validates chip-level test structures (JTAG, MBIST, scan/ATPG) to ensure silicon quality and manufacturability, collaborating with design and verification teams.
A Physical Design Engineer specializes in RTL-to-gate synthesis and physical implementation for high-speed communication chips, optimizing performance, power, and area while collaborating with cross-functional teams to resolve design bottlenecks and automate workflows using tools like Synopsys Fusion Compiler and Cadence Genus.
Design and implement FPGA/SoC solutions for high-speed communication and aerospace systems using HDL, embedded software, and verification tools.
Principal ECAD Library Engineer at Dell designing and maintaining Cadence Allegro/OrCAD symbols, footprints, and standards to ensure high-quality hardware development for laptops, servers, and peripherals.
Hardware Principal Engineer (Electrical Computer-Aided Design (ECAD) Library Engineer) The reputation of Dell Technologies for delivering award-winning hardware is legendary and our Hardware Engineering team is at the…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
Designs and implements ASIC/SoC RTL (Verilog/SystemVerilog) for high-performance SSD controllers, collaborating with verification, validation, and firmware teams to deliver next-gen enterprise and AI data center storage solutions.
Designs and integrates hardware components into Apple’s next-gen SoC, writing and merging RTL code, managing IP blocks, and ensuring timing closure with industry-standard tools.
Designs and verifies custom silicon for Google's TPU AI accelerators, focusing on SoC-level RTL, architecture, and integration within AI/ML systems.
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