Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Designs and verifies custom silicon for Google's TPU AI accelerators, focusing on SoC-level RTL, architecture, and integration within AI/ML systems.
Designs and implements advanced semiconductor testchips from RTL to GDSII tapeout, focusing on physical design, timing closure, and silicon validation for high-performance ASIC/FPGA solutions.
Design and integrate custom TPU silicon for AI/ML workloads, owning multi-chiplet SoC architecture, interposer planning, and RTL integration to deliver high-performance hardware at scale.
Senior engineer in San Jose designing and optimizing backend digital circuits using Cadence tools, scripting in Tcl/Python, and advising customers on best practices.
Designs and optimizes RTL-to-GDS semiconductor design flows for AMD’s embedded computing projects, maintaining synthesis, place-and-route, and physical signoff tools and methodologies.
Designs and optimizes advanced AI hardware chips from RTL to silicon, focusing on power, performance, and area in cutting-edge process nodes.
Leads chip-level floorplanning and power delivery network design for advanced AI hardware SoCs, balancing performance, power, and area while ensuring robust physical integrity.
Principal Physical Design Engineer at EnCharge AI in Bangalore builds and optimizes RTL-to-GDSII flows for sub-5nm AI hardware using Cadence tools, scripting, and deep PDK expertise.
Senior Physical Design Engineer at EnCharge AI in Bangalore optimizes AI hardware blocks from RTL to GDSII using Cadence tools, Tcl/Python automation, and PPA tuning for tape-outs.
Leads a small team to design and deliver high-performance AI hardware blocks, optimizing power, performance, and area while managing tape-out milestones using Cadence tools and advanced scripting.
Software Development Engineer Location: Bengaluru, India We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from…
FPGA Prototyping Staff Applications Engineer Location: Bengaluru, India We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We…
FPGA Prototyping/ Emulation Staff Application Engineer Location: Bengaluru, India We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive…
Sr Staff STA Application Engineer Location: Bengaluru, India We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver…
Soc Engineer (Physical Design) Location: Ho Chi Minh, Viet Nam We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from…
SerDes Analog Design Engineer, Sr Staff Location: Seongnam-si, Korea, Republic of At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive…
SOC Engineering, Sr Staff Engineer- RTL Design Location: Noida, India Job Title: SoC RTL Design Engineer, Sr Staff We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to…
Lead a team to verify low-power wireless SoC designs using SystemVerilog/UVM, ensuring robust IP and SoC solutions for edge connectivity applications.
Lead the physical design of AI SoCs and chiplets from RTL to GDSII, optimizing power, performance, and area using Synopsys/Cadence tools and guiding external partners.
Lead a global R&D team to design, develop, and debug software for the Innovus Implementation System, a physical design tool for ICs, using C/C++ in Linux and collaborating with customers.
We couldn't check your fit for this role — add a CV to your profile to see it next time.
