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Design and debug FPGA images for pre-silicon prototyping of ultra-low-power SoCs using Xilinx Vivado and Intel Quartus, supporting verification and software teams.
This role involves designing and verifying digital hardware, including ASICs and FPGAs, for defense applications using RTL design, simulation, and testbench development. The position requires U.S. citizenship and the ability to obtain a DoD Secret security clearance.
Staff Digital Design Engineer responsible for FPGA/ASIC RTL design, board-level schematic capture, and system architecture for aerospace and defense applications (electronic warfare, radar, communications) using Verilog/VHDL, high-speed interfaces, and PCB tools.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Overview: This role sits at the intersection of deep protocol expertise and direct partnership with our…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
We are seeking an FPGA Engineer to own the programmable logic in our humanoid robot's electronics. In this role, you will architect, design, and verify RTL for sensing, communication, and control functions, and…
Senior engineer leading FPGA system-level design creation, lab bring-up (60% of time), and validation for Microchip's semiconductor products, using Verilog/VHDL, C, and high-speed serial protocol expertise.
The Lead RTL Design & Validation Engineer will plan and execute the design and validation of DDR memory controller calibration solutions, including RTL logic and firmware routines. The role involves collaborating with cross-functional teams to ensure reliable memory initialization and performance across AMD's custom IP projects.
Develops FPGA/emulation models and tools for Pre-Si hardware/software verification, optimizing test environments and debugging RTL for Intel’s Pre-Silicon validation and Post-Silicon validation.
Lead Digital IP and subsystem development programs at NXP Semiconductors from planning through SoC integration release, driving cross-functional execution across architecture, design, and verification teams while building dashboards and metrics with tools like Power BI, SQL, and Jira.
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