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Designs and verifies high-speed protocol IP (e.g., PCIe, Ethernet) for emulation and prototyping tools using Verilog, UVM, and FPGA flows.
Senior Engineer designs and implements complex ASIC/SoC physical layouts, from floorplanning to tapeout, using Cadence tools and collaborating with RTL, verification, and packaging teams.
Senior Physical Design Engineer at Analog Devices in Bangalore, India, responsible for full-chip and block-level physical verification, signoff, and power integrity analysis for semiconductor designs.
ASIC Physical Design Engineer At Tektronix, we believe innovation starts with our customer. This approach has led us to a seventy-five-year history of delivering outstanding solutions to customers in virtually every…
Develops low-level system software and diagnostics for high-performance AI inference hardware, including firmware, drivers, and Linux kernel modules, with a focus on manufacturing test integration and hardware/software co-design.
Designs and automates test and debug features for complex AMD processors using scripting and AI/ML, ensuring scalable ASIC design flows.
Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.
Business Strategy Analyst Employment TypeFull Time LocationCA - SAN FRANCISCO Turn Insight into Impact - Join Us as a Business Strategy Analyst ActionLink is seeking a highly analytical and business-savvy professional…
FAST Lab – Entry Level FPGA Engineer Location: Merrimack, New Hampshire, United States Category: Engineering & Technology Employment Type: Full-Time Job Description Be a part of something bigger. At BAE Systems’…
Senior Principal FPGA Verification Engineer - $30K Sign On Bonus Location: Westminster, Colorado, United States Category: Engineering & Technology Employment Type: Full-Time Job Description Minimum $30,000 Sign On…
Leads a global team designing the microarchitecture and RTL for Graphcore’s AI accelerators, ensuring performance, power, and schedule targets while collaborating with architecture, physical design, and verification groups.
Designs and optimizes the physical layout of AI chips using advanced EDA tools and flows, ensuring high-performance and power-efficient designs for next-gen AI superchips.
Leads the design and deployment of system-level test solutions for next-generation AI processors, including hardware, software, automation, and characterization to support silicon bring-up and manufacturing.
Designs and implements micro-architecture and RTL for AI chips, collaborating with cross-functional teams to deliver high-quality silicon solutions using SystemVerilog/VHDL and EDA tools.
Designs and integrates advanced semiconductor logic for AI chips in Bengaluru, using SystemVerilog, Python, and digital design flows to deliver RTL and microarchitecture for Graphcore’s silicon.
Designs and optimizes the physical layout of advanced AI semiconductors using EDA tools, ensuring high-performance, power-efficient chips at leading-edge process nodes.
Build and deploy Salesforce solutions (Lightning, Flow, Apex, LWC) for CRM and digital marketing projects using Agile methods.
Physical Design - Sr Engineer Location: Chennai, Tamil Nādu, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
Lead Engineer/ Staff – RISCV Subsystem RTL Design Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group…
Security RTL Design Engineer-Sr Lead/Staff Location: Bangalore, India Department: Hardware Engineering Work Location: onsite Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group >…
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