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Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects!…
NVIDIA is looking for a Senior ASIC Verification Engineer to help verify our global IP! This position offers an opportunity to impact an array of products while collaborating with teams from design, architecture,…
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Designs and implements FPGA-based systems for clients, using Xilinx/Intel tools, RTL, and verification flows, while collaborating across hardware, software, and signal integrity teams.
Leads the design and delivery of FPGA-based security solutions using VHDL, Xilinx toolchains, and embedded software integration in a regulated environment.
Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this position, you will be working on advanced mixed-signal sensor circuits using state-of-the art process technology, as…
We are now looking for a Senior ASIC Engineer! NVIDIA is searching for an outstanding ASIC Engineer to build and implement an MMU for the world’s top SoCs and GPUs. This position provides an opportunity to influence a…
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About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities Responsible for scheduling, designing, developing, and supporting IP models of system…
Develop low-level firmware for a novel optical LLM accelerator, orchestrating hardware execution and optimizing performance for AI inference workloads.
Designs the digital architecture for mixed-signal power management systems in AI, datacenter, and high-performance computing, bridging analog sensing with control-loop decisions using ADC interfaces, DSP, and emulation models.
Leads verification of cutting-edge FPGA and ASIC solutions for PCIe and CXL-based IP, collaborating with global teams to ensure first-pass silicon success using UVM and SystemVerilog.
At Kepler Communications , we're not just imagining the future of on-demand space connectivity - we're leading it! Our mission is to provide real-time on-orbit connectivity for critical missions, enabling a new…
Designs and optimizes ultra-low-latency FPGA hardware and networking IP for financial trading systems, using VHDL/Verilog and tools like Xilinx Vivado.
Leads a team designing custom silicon and edge AI hardware for Google's products, using SystemVerilog and RTL development to optimize performance and integration.
Designs and executes verification plans for custom silicon components using SystemVerilog, UVM, and scripting languages to ensure high-performance, low-power hardware for Google's products.
Designs and integrates RISC-V CPU cores with custom extensions for ASIC chips in Bitcoin mining and AI cloud hardware, using Verilog/SystemVerilog and collaborating with cross-functional teams.
Designs and runs tests to validate Google’s TPU chips, focusing on the High Bandwidth Memory subsystem, from early planning through production silicon bring-up.
Design Verification Engineer at Bitdeer in Singapore who builds and runs test environments for ASIC chips and AI cloud hardware using UVM, SystemVerilog, and formal tools to ensure functional correctness before silicon.
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