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What We’re Looking For: We’re looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create…
Lead a team in Bangalore to define and scale physical design methodologies and CAD flows for Microsoft’s custom silicon (Azure Cobalt and Maia), driving AI-driven automation and first-pass silicon success.
Lead the architecture and RTL design of high-speed switching fabrics for next-gen memory and AI interconnects, guiding teams from spec to silicon bring-up.
About the team Our team is building industry-leading, highly efficient, and scalable video codec hardware solutions (FPGA and ASIC) from the ground up to better serve our billions of users. We are looking for strong…
Architects and implements power-analysis techniques for NVIDIA’s next-gen switches, using Verilog, Python, and industry tools to model and reduce chip energy consumption.
Internship assisting in the design and physical implementation of digital and mixed-signal ICs for power management and signal functions using ASIC tools like synthesis and P&R flows.
The application window is expected to close on: 10/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team The Common Hardware Group…
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: We are seeking a highly skilled and experienced IP Design Engineer to join our dynamic…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: Skills/Experience: Bachelor’s Degree required, Master or PhD degree in related field…
What We’re Looking For: We’re looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer.…
Designs and optimizes ASIC physical layouts using Cadence/ Synopsys tools, closing timing and power while driving tapeout readiness in a fast-paced chip startup.
Design AI/ML accelerator ASICs and storage solutions, defining I/O subsystems (PCIe/UCIe/CXL) and memory hierarchies for high-performance AI workloads.
Design and develop secure hardware IPs like post-quantum crypto accelerators and random number generators using Verilog/VHDL and ASIC flows.
Design and integrate secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, UPF, and cryptographic engines.
Designs and integrates secure ASIC subsystems to protect Apple’s SoCs from side-channel attacks and ensure data integrity using RTL, cryptographic engines, and hardware defenses.
Lead verification of Cisco’s cutting-edge data-center ASICs, building DV environments, writing test plans, and ensuring full coverage with Verilog/SystemVerilog/UVM while collaborating with designers and software teams.
Designs and verifies integrated circuits for ASIC development, including architecture, logic design, and system simulation, with a focus on timing and power efficiency.
Principal Digital Design Engineer designing secure embedded controllers and cryptographic hardware for automotive, industrial, and defense markets using ASIC/FPGA flows, Verilog/VHDL, and security countermeasures.
We are now looking for an ASIC Top Floorplan Design Engineer. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and implement the world’s leading SoC's and GPU's. This position offers you a unique…
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