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Job Details: Job Description: The Role and Impact As a SoC Logic Design Engineer, you will play a pivotal role in developing and integrating logic designs into complex System-on-Chip (SoC) architectures. Your…
Company: Qualcomm Israel Ltd. Job Area: Engineering Group, Engineering Group > Modem Technologies General Summary: S enior Staff RTL Design Engineer - Haifa or Hod HaSharon As an RTL Design Engineer, you would be…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: BDC WRD (Wi-Fi) is responsible for developing Qualcomm’s Wi-Fi chips. We are looking for…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 8 to 11 years of work experience in ASIC/SoC Design Experience in Logic design…
Join a Team That Builds the Future of Computing At IBM’s largest European R&D site in Ehningen, Germany, innovation is a team effort. With 1,300 employees and around 200 engineers in our hardware development team,…
Design signal processing-intensive RTL for wireless communication SoCs as part of Apple's wireless silicon team, focusing on energy-efficient design and diverse connectivity technologies.
Lead end-to-end digital design and verification for mixed-signal SoCs at the Chandler site, driving strategy, methodology standardization (UVM, formal, AMS/DMS), and team scaling.
Principal AI Silicon Architect designs and optimizes hardware architectures for AI workloads, collaborating with software and hardware teams to deliver high-performance, scalable cloud infrastructure at Microsoft.
Apple is offering GPU internships in the UK focused on RTL design, power optimization, and physical design for Apple Silicon. Interns will collaborate with engineering teams on chip architecture, power analysis, and ASIC design flows using languages like C++, Python, and Verilog.
The Staff/Sr Staff Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within Renesas MCU products. The role involves collaborating with cross-functional teams to ensure PPA targets are met using industry-standard EDA tools.
The Principal Engineer will lead RTL design and micro-architecture development for complex IP and subsystems within MCU SoCs. The role involves collaborating with cross-functional teams to ensure PPA targets are met while mentoring junior engineers and improving design methodologies.
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Digital Design Engineer responsible for SoC/MCU digital sub-circuit development including RTL coding in Verilog/SystemVerilog, synthesis, STA, formal verification, DFT, and post-silicon validation at NXP's Catania site.
Lead the full digital IC design flow for complex SoC microcontrollers at NXP's Catania site, from architecture through RTL coding (Verilog/SystemVerilog), synthesis, STA, formal verification, and post-silicon debug.
This internship role involves assisting with the design, simulation, and verification of digital integrated circuits using Verilog or VHDL. Interns will work on FPGA prototyping, digital modeling, and timing analysis alongside experienced engineers.
Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum Qualifications: 2 to 8+ years of solid experience in IP/SoC design and…
Who we are CryptoNext Security is a deeptech startup specializing in post-quantum cryptography. Our solutions help businesses and institutions prepare for a future where quantum computers will challenge traditional…
SyoSil is hiring ASIC/FPGA design and verification engineers to work on RF radio ASIC projects using SystemVerilog and UVM. The role involves full-cycle IP block development, from architecture to verification, within a collaborative, SCRUM-based international team.
RTL design and integration engineer on AMD's FPGA product team, driving silicon implementation using Verilog/SystemVerilog, EDA tools, and scripting automation.
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