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Staff Subsystem Design Engineer Job Overview Arm’s IP and Technology team in Solutions Engineering department evelop subsystem solutions and SoC IPs for next-generation systems targeting Edge AI, Physical AI and Cloud…
Architect and optimize the next-generation SystemVerilog compiler for Xcelium, enabling faster verification of billion-gate AI and hyperscale chip designs using C++ and compiler theory.
Manage a team of 10–15 embedded software engineers developing real-time communications systems for defense programs like F-22, F-35, and Link16 radios.
Design and verify FPGA hardware using VHDL for radar, RF/EO DSP, and embedded systems; collaborate with systems engineers and verify designs with constrained-random tests.
Designs and integrates embedded real-time software for aerospace/defense systems, focusing on firmware-hardware integration, RTOS, and mission-critical avionics with C++ and security constraints.
Leads hardware/software co-verification for SoC devices using emulators (e.g., Cadence Palladium) and FPGAs, bridging RTL porting, firmware development, and system-level testing across pre- and post-silicon phases.
Design and run verification tests for next-gen DRAM and memory chips using SystemVerilog/UVM, debug failures, and automate flows to ensure silicon meets specs.
Lead the design and delivery of next-gen silicon-photonics integrated circuits for NVIDIA’s AI supercomputers, owning architecture through tapeout and validation.
Senior Electrical Engineer verifies FPGA-based radar designs using SystemVerilog/UVM testbenches and industry simulators, ensuring functional correctness and coverage.
Senior Embedded Firmware/Flight Software Engineer Psionic, Inc. is a startup focused on lidar sensors for autonomous systems. We value our customer relationships, our diverse and dynamic work environment, and our…
Lead verification of AMD’s IOHUB subsystem, defining test plans and closing coverage for high-performance interconnect IP used in CPUs, GPUs, and data-center hardware.
About the role Lead the micro-architecture and RTL design for Mixed-Signal chiplet focused on intelligent power optimization solutions for AI and high-performance computing. What you'll do Micro-architect and own…
Embedded Software Engineer Who we are: EOI Space is developing and deploying a constellation of satellites in Very Low Earth Orbit (VLEO) to provide ultra-high-resolution Earth imagery. We aim to deliver timely and…
Senior FPGA engineer building hardware prototypes and validating next-gen satellite communications ASICs, from FPGA bring-up to first-silicon debug.
Develop low-level firmware in C and assembly for Apple’s SoC components, implementing critical features for upcoming devices.
Develops and optimizes FPGA-based DSP algorithms for navigation systems, beamforming, and high-speed signal processing using VHDL/Verilog and Xilinx/Intel toolchains.
Design and debug embedded electronics for airborne, maritime, and ground-based electro-optical systems, including real-time video, motor control, and power regulation, from schematic to production support.
Designs and optimizes custom silicon for Google Cloud, focusing on performance, power, and area while collaborating with cross-functional hardware teams.
Design and optimize FPGA-based hardware for ultra-low-latency trading infrastructure, integrating Ethernet stacks and custom logic to parse and route exchange data efficiently.
Build and deploy AI agents that automate silicon IP design workflows using RAG, structured tool execution, and EDA tool integration to accelerate spec-to-netlist cycles.
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