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Analog & Mixed-Signal ASIC Design Engineer At Tektronix, we believe innovation starts with our customer. This approach has led us to a seventy-five-year history of delivering outstanding solutions to customers in…
Designs and integrates hardware components into Apple’s next-gen SoC, writing and merging RTL code, managing IP blocks, and ensuring timing closure with industry-standard tools.
Designs and verifies analog and mixed-signal integrated circuits for power systems, from concept to post-layout, using Cadence tools and collaborating across teams.
Lead the design and delivery of high-speed ASICs for optical data transmission, overseeing chip architecture through mass production and global team coordination.
Principal Engineer in Marvell’s Design Verification team, building and running testbenches to verify high-speed storage IP like read channels and cryptographic engines using SystemVerilog/UVM and EDA tools.
Designs and automates AI/ML-driven chip design flows to optimize power, performance, and area for NXP’s SoCs and processors using Python/C++ and advanced ML techniques.
Design Verification Engineer at AMD responsible for developing and maintaining tests to verify complex processor architectures and ASIC/SOC designs using Verilog, SystemVerilog, and UVM.
Designs and codes FPGA logic in VHDL for radar and electronic-warfare systems, verifies designs in lab environments, and maintains documentation for production hardware.
Designs and implements ASIC physical layouts for Cisco’s advanced networking chips, using RTL-to-GDS flows, place-and-route, and timing closure in a collaborative VLSI team.
Engineer regulatory compliance for Cisco’s wireless and networking hardware, defining EMC/RF requirements, running pre-compliance tests, and guiding design fixes to meet global certifications like FCC, CE, and RED.
Designs and verifies ASIC/FPGA chips for high-speed optical transmission systems, using VHDL/Verilog and industry tools to optimize performance and power in coherent networking hardware.
Design and verify ASICs for HP printers, leading RTL coding, verification, and silicon validation while collaborating with cross-functional teams to deliver embedded solutions.
The NOKIA Optics Subsystems group develops the front-ends for coherent optical long-distance transmission modules to interconnect network nodes and data centers. We are expanding and looking for highly motivated and…
Crane Aerospace and Electronics has an exciting opportunity for an Electrical Engineer II at our Lynnwood, WA location. About Crane: Crane Aerospace & Electronics supplies critical systems and components to the…
Designs and implements automated test and debug features for AMD's complex processor and GPU chips, using scripting and AI/ML tools to improve chip reliability and performance.
Designs and integrates high-performance, low-power pixel processing ASICs for Apple’s SoCs, collaborating across teams to deliver functional multimedia IP for millions of devices.
Develops and tests control-plane and data-plane software for Cisco’s Silicon One network processors using C++ and Python, focusing on multicast and L2/L3 networking features.
Lead a software engineering team in Bangalore that builds and delivers SDKs for Cisco’s next-gen networking ASICs, collaborating with global engineering and customers.
Designs and automates ASIC development workflows using AI/ML techniques to improve power, performance, and verification for NXP's SoC and IP teams.
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