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Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission.…
Kandou is a semiconductor company pioneering high-performance interconnect and chip-to-chip communication solutions. Our engineering teams push the boundaries of what is possible in silicon design, validation, and…
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems - a critical barrier to scalable…
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable…
Join a high-impact team developing next-generation automotive SoCs. Contribute to NoC IP integration, RTL design, connectivity validation, and automation , while collaborating with architecture, verification, and…
CPU Core MicroArchitect/RTL Design Engineer crafting functional units for AMD's next-generation processor cores, with a primary focus on caches and memory subsystem RTL design and coding.
#WeAreIn for jobs that impact everyone's life. Build the future nobody’s dreamed of yet... are you ready to rethink the impossible? As a Staff Digital Design Engineer in our Research & Development team,…
The SMTS Silicon Design Engineer will develop host controller IP for high-speed I/O technologies using Verilog HDL. This role involves designing, verifying, and mentoring junior engineers to support next-generation high-performance computing and AI products.
DFX RTL design engineer on AMD's Client SOC DFX team, planning and implementing DFX features (JTAG, Scan, Boundary Scan, Debug) and low-power UPF support for next-gen microprocessors using Verilog/SystemVerilog/VHDL and scripting languages.
About Ethernovia, Inc. Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics and other intelligent machines. Founded in 2018,…
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
Principal FPGA Design Engineer at Microchip's Chandler Design Center developing and validating FPGA-based platforms for next-gen USB and Ethernet PHY products using Verilog/SystemVerilog RTL design, Vivado, and lab debug equipment.
Designs and verifies FPGA logic for Microchip PolarFire SoCs using VHDL/Verilog, integrating with RISC-V cores and Linux/RTOS drivers.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Lattice Overview There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers.…
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description This role offers a position in system power management IP cores and…
Memwize is a VC-backed, stealth-mode startup building rack-level AI inference systems . We are seeking an experienced RTL Design Engineer to implement RTL blocks in close collaboration with architects and…
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
Configure and integrate RISC processor IP into SoC platforms, customize processor features, develop RTL wrappers and system glue logic, integrate interconnects and interrupt controllers, support verification and system…
Lead physical design (RTL-to-GDS) for AMD’s next-gen AI and high-performance ASICs, driving PnR, timing closure, and tape-outs while collaborating with architects and EDA vendors.
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