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Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
Lead a team of engineers to design and ship complex C++ features for Jasper, Cadence’s formal verification platform, while mentoring junior developers.
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
Designs and implements FPGA logic for optical telecommunication products, collaborating with hardware and firmware teams to validate and optimize high-speed data transmission systems using Verilog/SystemVerilog and AMD/Xilinx or Altera tools.
Lead a team building EDA software in C/C++/TCL on Linux, focusing on semiconductor device simulation and analysis flows like SPICE, timing, and power.
Designs and leads the development of high-performance microcontrollers for edge AI applications, using Verilog/SystemVerilog, synthesis, and verification tools.
Lead a team building a distributed, multi-threaded physical synthesis engine for IC design tools, collaborating with global R&D and customer-facing teams using C/C++ on Linux.
Lead a team building a distributed, multi-threaded physical synthesis engine in C++ for Cadence’s Innovus Implementation System, collaborating with global R&D and supporting customers.
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Engineer II Systems (HPC) Location: India - Chennai Time Type: Full time Job Description Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the…
Physical Design Expert We’re looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, responsible for developing both Technology Methodologies & Flows for all products…
Tech Lead Physical Design Engineer, Power Integrity Location: San Jose, California, United States Department: ASIC Engineering Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built…
Principal Design Engineer Location: SHANGHAI Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Key Responsibilities…
Software Engineer II (C++) Location: FELDKIRCHEN (Munich), CAMBRIDGE 03 Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.…
Lead Design Engineer Location: CARY, SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. We offer amazing…
Software Engineer II, Synthesis Location: SAN JOSE Time Type: Full time Job Description At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design…
Physical Design Engineer - Block Level, Subsystem Implementation Department: ASIC Location: San Jose Compensation: $200K – $300K • Plus Significant Equity Employment Type: FullTime About Etched Etched is building…
Physical Design Engineer - Flow & Methodologies Department: ASIC Location: San Jose Compensation: $200K – $300K • Plus Significant Equity Employment Type: FullTime About Etched Etched is building hardware for…
Designs and validates electrical and functional architectures for space-based electro-optical sensors, integrating hardware/software and managing telemetry, telecommands, and system tests for Earth observation or scientific missions.
Digital Design Engineer Location: Santa Clara, CA Department: External - Client Requirement Job description : Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for…
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