Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
Build and lead a new automation platform for SoC chassis design, translating architecture specs into generated RTL, registers, and verification collateral using Python and templating systems.
We are looking for an FPGA Engineer to join our team and work on high-performance FPGA/SoC solutions, with a strong focus on digital signal processing (DSP), algorithms, and RF applications . Location This is a…
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Hardware Engineer Intern contributing to FPGA development and hardware improvements at a global trading firm, using VHDL/Verilog and collaborating with trading and tech teams.
Lead formal verification for AMD’s I/O and SoC designs, defining methodologies and mentoring engineers to ensure silicon quality for next-gen processors and AI systems.
At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training…
Designs and verifies PCIe subsystems and SoC infrastructure for Google’s next-gen TPUs, focusing on high-performance AI hardware acceleration.
Principal engineer leads a small team designing high-performance FPGA/ASIC Front Haul Gateway solutions for cellular infrastructure radios, using Verilog, SystemVerilog, and AMD Vivado tooling.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions…
Principal backend engineer designs ASIC digital logic and microarchitecture using Verilog and Cadence tools in a semiconductor software team.
Principal digital back-end engineer designs and verifies ASIC flows using Cadence tools, focusing on RTL, synthesis, timing, and physical design for high-performance semiconductor IP.
Designs and evaluates backend integrated circuits for AI processors, using EDA tools and circuit simulation to optimize performance.
Senior engineer verifying next-gen microprocessor interconnects using SystemVerilog/UVM testbenches and industry tools to ensure functionality and performance before silicon tape-out.
Leads RTL microarchitecture design for an AI-focused company, defining hardware blocks and optimizing chip performance for machine-learning workloads.
Designs and verifies RTL (Register Transfer Level) logic for AI hardware accelerators using Verilog/VHDL and industry-standard EDA tools.
Lead RTL microarchitecture design for GPU, DSP, and AI accelerators in complex SoCs, optimizing performance, power, and area while guiding cross-functional teams.
Designs and implements RTL for AI accelerators and ASICs, optimizing for performance and power efficiency.
Pre-Silicon Validation Engineer Location: India Department: Weekday's Client via platform Workplace: remote Employment Type: full Description This role is for one of the Weekday's clients Min Experience: 6+…
Designs and verifies RTL for AI accelerators and ASICs, optimizing hardware for machine-learning workloads.
We couldn't check your fit for this role — add a CV to your profile to see it next time.