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We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Description RF Front-end EM Design Co-Op Location: Irvine, CA Term: January - June 2027 (Full-Time Co-Op) About the Role We are seeking a highly motivated RF Front-End EM Design Co-Op to join our team in Irvine,…
Overview of Role We are seeking a highly motivated mmW/RF/Analog Circuit Design Engineer to join TSMC’s RF design team and pioneer the use of advanced technology nodes in RF and mmWave circuit design. This role is…
Senior digital IC design engineer at ams OSRAM's Plano, TX site who designs, verifies, synthesizes, and brings up silicon for sensor/imaging mixed-signal semiconductors. Core stack: Verilog/SystemVerilog, UVM, low-power and CDC/LEC flows, and Cadence tools like Xcelium, Genus, SpyGlass, and JasperGold.
ams OSRAM in Premstätten, Austria is hiring an IC Package / PCB Layout Engineer to design IC package substrates and PCB layouts for semiconductor products using Cadence Allegro/Virtuoso and/or Altium Designer. Requires 6+ years in the semiconductor/electronics industry with experience in HDI, BGA, wirebond and flip-chip packaging.
ams OSRAM is hiring an IC Package / PCB Layout Engineer in Premstätten, Austria, to design IC package substrates and HDI PCBs using Cadence Allegro and/or Altium Designer. The role requires 6+ years in the semiconductor industry, plus knowledge of signal integrity, ESD/EMC, and packaging technologies like BGA, wirebond, and flip-chip.
A paid co-op (Summer/Fall 2027) at Skyworks' Cedar Rapids design center where a student designs reusable analog IC building blocks (charge pumps, bandgap references, voltage regulators, op-amps, DACs) for next-generation cellular phone chips, working alongside a mentor and using simulation tools like Cadence Virtuoso and SPICE.
A co-op intern on Skyworks' Filter Automation team will build Python-based automation for the design, verification, and tapeout flows of SAW/BAW acoustic filters, integrating EDA tools like Keysight ADS, Cadence Virtuoso, HFSS, and Calibre. The role involves creating tools, dashboards, and GitHub-based workflows to improve engineering productivity.
Position Summary: We are seeking a highly skilled Senior Analog Layout Engineer to lead the physical layout of complex analog, mixed‑signal, and high‑performance IC designs. This role requires deep expertise in custom…
Kyocera is hiring a Senior Principal Engineer in San Diego to lead end-to-end design of mmWave RFICs — owning the Tx signal chain (mixers, LO distribution, PAs, beamforming, calibration) for 5G FR2/FR3 and FMCW/pulse radar, from architecture and Cadence-based circuit design through verification, lab characterization, and production ramp, while mentoring engineers.
Kyocera is hiring a Senior RFIC Design Engineer in San Diego to design and verify high-performance RF, analog, and mixed-signal integrated circuits for wireless and sensing products — from architecture and transistor-level design through layout, simulation, silicon characterization, and production ramp — using tools like Cadence Virtuoso and Spectre.
Kyocera is hiring a Principal RFIC Design Engineer in San Diego to architect, design, verify, and ramp high-performance RF/analog/mixed-signal SoCs for wireless and sensing products. Day-to-day is hands-on circuit design (receivers, transmitters, PLLs, analog baseband) using Cadence Virtuoso/Spectre, plus silicon debug, layout guidance, and cross-functional technical leadership through production.
Our goal is to make everyday life and industry smarter and more prosperous by advancing lithium-ion battery control ICs. The applications for our technology continue to expand across PCs, mobile devices, industrial…
Change the world. Love your job. Texas Instruments is seeking a Layout Design Manager. In this role, you will be leading a team developing power management ICs for high power density applications. This role combines…
About GlobalFoundries GlobalFoundries (GF) is a leading manufacturer of essential semiconductors, enabling AI at scale from the cloud to the physical world. Through deep partnerships with customers, GF delivers…
How do you design memory technology that delivers high performance while keeping power consumption and silicon area to a minimum? At Xenergic, it starts with a deep understanding of analog circuits, advanced…
Develops Lightmatter's internal photonic Process Design Kit: Python-based parametric cells and physics-based behavioral models for photonic devices, validated against silicon measurements, with CI/regression to keep layout, netlists, and models in sync. Heavy Python (NumPy/SciPy) plus EDA tools like Lumerical INTERCONNECT and Cadence Virtuoso.
About the Role: We are seeking a highly experienced and deeply hands-on Staff Validation Engineer to join our dynamic Silicon Validation team in Bengaluru. In this critical role, you will serve as a technical lead and…
Come join Analog Devices (ADI) – a place where Innovation meets Impact. For more than 55 years, Analog Devices has been inventing new breakthrough technologies that transform lives. At ADI you will work alongside the…
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