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Program Manager leading the end-to-end lifecycle of automotive networking chip (ASIC/SoC) development at Ethernovia — planning schedules, budgets, and cross-functional execution from concept to silicon, while ensuring ISO 26262, ISO/SAE 21434, and ASPICE compliance and managing key customer relationships.
RTL Design Engineer building AI chips that are hard-coded for specific machine learning model architectures. Day to day centers on developing and implementing design verification strategies for existing and upcoming ASIC designs, working closely with state-of-the-art ML architectures.
Fidus Systems, an electronics design services firm, is hiring an FPGA Designer (hybrid in Ottawa or Kitchener-Waterloo) to architect and build complex FPGA/CPLD systems for clients: RTL design in Verilog/VHDL, IP integration, simulation, timing closure, and lab bring-up/debug. Requires 5+ years of FPGA experience with Xilinx/Intel toolchains. Salary $125k–$160k CAD plus benefits.
About NETINT Technologies Inc. NETINT Technologies is a pioneer of computational storage and video processing SoC solutions for cloud and edge computing. Its Codensity portfolio enables enterprise, cloud data centers,…
NETINT Technologies, a Canadian computational storage and video-processing SoC startup, is hiring an IC Design Engineer in Burnaby or Markham. Day to day you design and verify SoC sub-systems: micro-architecture and IP selection, RTL coding in Verilog/SystemVerilog, FPGA builds with Xilinx Vivado, and HW/FW bring-up, debugging and system validation.
Senior digital design engineer at Renesas in Bengaluru who owns micro-architecture and front-end RTL for digital blocks in power-management ASICs, taking designs from spec through synthesis, STA, DFT, and silicon debug. Core stack: Verilog/SystemVerilog, CDC handling, I2C/PMBUS protocols, low-power design.
Overview The System Director Manager for Optical Digital DSP base Systems is a senior leadership role responsible for managing and directing the development, implementation, and optimization within optical…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Sr Application Engineer – Digital Implementation & Physical Design Location: Malaysia Job Overview We…
About the Company Retym is an innovative semiconductor startup developing next-generation chips for high-speed communication systems. Our mission is to redefine performance and efficiency in data transmission through…
Anello Photonics is hiring an FPGA Design Engineer in Santa Clara, CA to design, verify, and bring to production FPGA-based hardware for its next-generation photonic navigation products. Day to day: RTL design and simulation (Verilog/SystemVerilog/VHDL), timing closure, hardware bring-up/debugging, and cross-functional collaboration through production.
About GlobalFoundries: GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology…
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software…
Change the world. Love your job. In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high…
Job Details: Job Description: Devices Development Group Malaysia (DDG-MYS) Client SoC Team is seeking highly motivated engineering talent to join Intel’s next-generation Client SoC development team as a SoC RTL/Logic…
NVIDIA is hiring a Senior ASIC Design Engineer in Santa Clara to architect, implement, and verify high-performance, power-efficient RTL for its SoCs and GPUs. Day to day this means RTL design and synthesis, logic and timing verification, and testbench development using Verilog/SystemVerilog, Perl/Python, and tools like VCS, Verdi, and GDB.
Builds and owns the methodology, tooling, and AI-powered workflows used by every designer on AMD's next-generation CPU core RTL team — including LLM-based assistants, linting/static-analysis flows, and SystemVerilog parsing and code-analysis tools — collaborating with verification, physical design, and post-silicon teams.
Front-end ASIC design engineer at Credo Technology Group who architects, implements, and verifies complex logic blocks for high-speed connectivity chips, supporting integration tasks (Lint, CDC, synthesis, ECO) through tape-out. Core technologies: Verilog/SystemVerilog RTL design and verification, UVM, and scripting in Python, Tcl, Perl, and shell.
About GlobalFoundries GlobalFoundries (GF) is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology…
Senior technical lead role in GlobalFoundries' IP Engineering team in Hsinchu, Taiwan, driving development and delivery of high-performance compute processor IP — from architecture and microarchitecture through RTL design, UVM/formal verification, and signoff — while mentoring engineers and leading execution across global multi-site teams using SystemVerilog, C/C++, Python, and EDA toolchains.
IC design verification engineer on Snap's Spectacles team, verifying display integrated circuits for AR eyewear by building UVM/assertion-based testbenches, executing coverage-driven verification plans, and automating flows. Core stack: SystemVerilog/UVM, Siemens Questa, Verilog RTL, and TCL/Python/Perl/Shell scripting on Linux, working on-site 4+ days per week.
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