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Renesas is seeking a Senior Digital Design Verification Engineer to join our team developing complex power management SoCs. These products integrate digital control, telemetry, fault management, communication…
Designs and implements complex FPGA/RTL designs (Verilog/SystemVerilog, Vivado, Zynq/Ultrascale+/Versal) for CHAOS Industries' next-generation radar sensor products, covering the full FPGA lifecycle through timing analysis, hardware integration, and support of deployed systems. Full-time on-site in Hawthorne, CA.
Senior embedded SW/firmware engineer designing and implementing complex FPGA/RTL designs for CHAOS Industries' next-generation radar sensor products, integrating them with software systems and supporting deployed capabilities. Full-time on-site in Hawthorne, CA, working in Verilog/SystemVerilog with the AMD (Xilinx) Vivado toolchain and SoC FPGAs.
Front-end ASIC design engineer responsible for RTL implementation and verification of complex logic blocks, supporting synthesis, DFT, STA, tape-outs, and chip bring-up at a high-speed interconnect semiconductor company. Core tech includes Verilog/SystemVerilog, Serdes, Ethernet, UVM, and timing analysis.
Sr. FPGA Design Engineer on the flight software team at Reliable Robotics, designing, simulating, synthesizing, integrating, and testing FPGAs for the flight computer and air-to-air radar in its aircraft autonomy stack. Core skills: VHDL/Verilog/SystemVerilog and industry-standard FPGA design, simulation, and synthesis tools.
Designs and implements low-latency digital systems for a silicon photonics-based quantum computer, using FPGAs, SystemVerilog, and Python.
Designs, implements, and validates FPGA-based digital microarchitectures using Verilog/SystemVerilog for quantum computing systems in Palo Alto.
Design Verification Engineer at MatX, an AI-chip company, owning subsystem- and chip-level verification of high-performance AI accelerator silicon: building testbenches and tests, driving coverage closure, and leading verification sign-off through design freeze and tapeout using SystemVerilog/UVM, formal and simulation, plus Python/C++.
Senior ASIC Design Engineer Celero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products…
1. 从RTL创建和维护Emulation/FPGA模型，将芯片项目Porting到原型平台(Emulator和FPGA), 交付EMU DB/FPGA bitfile到原型验证团队 2. 为Emulation/FPGA场景创建独立的测试冒烟用例。 3. 在Emulation/FPGA平台上Bring up外部接口（例如，DDR，PCIe，USB, 以太网等）。 4.…
1. 负责 RISC-V IOMMU IP 的架构定义、微架构设计及RTL实现，确保满足芯片对设备内存的管理需求，满足项目PPA 要求。 2. 深入理解并实现 RISC-V IOMMU 架构规范，支持多级页表地址转换及权限管理，支持虚拟化扩展。 3. 负责 IOMMU IP 与 SoC 系统的集成，处理与 CPU、DMA、NoC 及 DDR 控制器的交互，满足 SoC 架构需求。 4. 主导 IP…
AI SoC前端设计工程师，专注于高性能IP设计与优化。该职位将参与SoC关键IP设计、优化和集成，推动AI SoC的高效能、高安全性与低功耗设计。 1、负责AI SoC关键IP设计，负责RTL设计与优化，确保IP的高效实现，满足PPA（性能/功耗/面积）需求 2、 参与IP设计验证，制定测试计划，支持功能验证和性能优化 3、与SoC架构团队合作，定义IP功能需求和SoC级集成方案…
该职位负责高性能RISC-V CPU子系统外围模块的集成和测试点分解。具体职责包括： 1. 根据服务器CPU 调试场景，定义RISC-V Debug/Trace 特性和架构，并完成RTL集成和测试点分解 2. 根据服务器CPU中断处理的软/硬件场景，定义RISC-V AIA模块的特性和架构，并完成RTL集成和测试点分解 3. 根据服务器CPU内存管理的软/硬件场景，定义RISC-V IOMMU特性和架构，并完成RTL集成和测试点分解…
Team Credo is seeking a Sr. Staff Design Engineer to drive both hands-on digital ASIC design and strategic architecture direction for our High-Performance Network Interface IP portfolio. This role has direct impact on…
Senior FPGA engineer implementing digital signal processing for software-defined radios on Zynq UltraScale+ MPSoC, using MATLAB/Simulink, VHDL/Verilog, and Xilinx Vivado in a hybrid role based in Boston or Scottsdale.
FPGA Engineer at a MilTech product company with its own R&D and production facilities, based in its Kyiv office. Day to day: developing and optimizing DSP algorithms on FPGA for navigation and communication signals, integrating them with RF frontends and embedded control systems, using Verilog/SystemVerilog plus MATLAB/Simulink or Python for algorithm modeling.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
Центр квантовых технологий Сбера разрабатывает собственные ускорители вычислений и создает для них FPGA-прошивки. Команда работает с высокочастотными многоканальными АЦП и ЦАП, высокоскоростными интерфейсами и…
FPGA engineer on a high-frequency trading team, designing and optimizing hardware for ultra-low-latency trading systems — protocol parsing, order entry, market data processing, timing closure and latency tuning. Core stack: Verilog/SystemVerilog, Xilinx Vivado / Altera Quartus, ILA/SignalTap debug and Questa/ModelSim simulation. Fully remote worldwide.
