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1. 负责top floorplan，电源网络，partition， 时钟树， IO assignment 等规划 2. 建立后端sign off spec，signoff 策略 和signoff checklist，包括STA, EM/IR, PV 等 3. 负责先进工艺中后端流程开发 4. 负责关键ip的ppa 优化 5. 与前端构架深入合作，保证构架设计可实现性与ppa 优化 1.…
面向高性能SRAM, 基础IP或标准单元（如触发器、脉冲锁存器、逻辑触发器、特殊复杂单元等）的设计、验证及库生成。与晶圆厂开展DTCO（设计/工艺协同优化） 针对性能、功耗和面积（PPA）以及良率优化SRAM/定制电路。 开发定制版图并执行物理验证（例如，DRC、LVS）。 开展大量电路仿真，以验证SRAM的功能与性能、电气完整性及鲁棒性。 …
● 负责SOC、subsystem 逻辑综合、DFT merge、形式验证、STA signoff等工作。 ● 和前后端团队合作，完成芯片设计过程中 clock/reset方案，low power和power domain划分方案，时序收敛等工作。 ● 熟悉SDC、timing check、VCLP/CLP check，成为流片前timing质量把关人。 ● 电子、计算机等相关专业，硕士及以上学历，3年及以上SoC逻辑综合经验。 ●…
Team Credo is seeking a Sr. Staff Design Engineer to drive both hands-on digital ASIC design and strategic architecture direction for our High-Performance Network Interface IP portfolio. This role has direct impact on…
Senior FPGA engineer implementing digital signal processing for software-defined radios on Zynq UltraScale+ MPSoC, using MATLAB/Simulink, VHDL/Verilog, and Xilinx Vivado in a hybrid role based in Boston or Scottsdale.
Senior embedded firmware engineer at Camlin's Real-Time Applications unit in Kraków (on-site): designs, develops, and optimizes real-time DSP and microcontroller firmware in C/C++ on RTOSes like FreeRTOS and Zephyr, meeting strict latency constraints, while mentoring junior engineers and stepping into technical leadership.
ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world’s most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies…
The Care Manager l-TCL assures that individuals and families with special health care needs receive integrated whole-person care management, including coordinating across physical health, behavioral health, pharmacy…
FPGA engineer on a high-frequency trading team, designing and optimizing hardware for ultra-low-latency trading systems — protocol parsing, order entry, market data processing, timing closure and latency tuning. Core stack: Verilog/SystemVerilog, Xilinx Vivado / Altera Quartus, ILA/SignalTap debug and Questa/ModelSim simulation. Fully remote worldwide.
Imagine what you could do here. At Apple, new insights have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There’s no telling what you could accomplish at…
Senior DFT engineer/expert at Alibaba's T-Head chip division in Shanghai: defines DFT/DFD architecture, implements SCAN/MBIST/boundary-scan logic, closes timing, develops production test patterns, and builds DFT CAD tool flows. Key stack: Verilog/SystemVerilog, DFT tools (TetraMax, TestKompress, Tessent), Tcl/Python/Perl.
Full-Time Commercial Journeyman Electrician Job Posting We are TCL Electrical & Lighting, a fast growing, highly regarded commercial electrical and lighting service provider, located in North Aurora, IL, offering…
Normal Computing | Build with Us Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure,…
Leads block- and subsystem-level physical design closure (timing, congestion, power integrity, clocking) for complex hierarchical SoCs at advanced nodes, aligning subsystem implementation with SoC-level strategies. Works with Synopsys ICC2/Fusion Compiler/PrimeTime and Cadence Innovus/Tempus, automating with Tcl/Python/Perl.
Basic Qualifications Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's…
Senior Physical Design Engineer responsible for full-chip and block-level physical implementation (RTL to GDSII) of next-gen transceiver IPs at TSMC 3nm/5nm nodes, using tools like ICC2, Innovus, and Calibre, with a focus on timing/power closure and tapeout signoff.
Designs and develops advanced-node CMOS integrated circuit layouts, focusing on high-speed analog blocks like PLLs and ADCs while ensuring DRC/LVS compliance and minimizing parasitics.
Designs advanced-node CMOS IC layouts (PLL, ADC, regulators, etc.), ensuring DRC/LVS compliance, minimizing parasitics, and optimizing yield and performance.
As a Sr Advanced Test Engineer here at Honeywell Aerospace, you will be part of a team that designs, develops, integrates, and maintains highly complex test consoles used for testing reaction wheels and control moment…
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