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Design and verify ASIC/FPGA hardware for defense systems, writing RTL, running simulations, and integrating modules in a lab using Xilinx/Altera tools and scripting.
Designs and verifies FPGA hardware using VHDL/Verilog/SystemVerilog, UVM testbenches, and Xilinx tools, while guiding a remote verification team on DO-254 processes.
Note: This position is posted for Markham, but it is open to candidates across Canada, including Mississauga, Nepean, and Ottawa. The role can be hybrid or fully remote depending on your location and preference. We Are…
**Please note this role is only open to candidates currently located in and with working rights in the DE** Location: Preferably based in Munich. Seniority: Engineer, Senior Engineer Welcome to Codasip At Codasip,…
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Design and verify integrated circuits for AR display systems, building UVM-based testbenches and using Siemens Questa for simulation and debug.
NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position offers you an outstanding opportunity to influence…
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping…
NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading SoC's and GPU's. This position offers the opportunity to have real impact in a dynamic, technology-focused…
Senior engineer building automation tools and methodologies to accelerate NVIDIA’s ASIC and SoC chip design flows, working with EDA vendors and RTL teams.
Designs and verifies RFIC and mixed-signal ASICs for a space-based 6 Tbps satellite network using Cadence Virtuoso and Spectre RF.
Designs and optimizes high-performance coherent interconnect IP and last-level cache blocks for Samsung's advanced semiconductor products, collaborating with architects, verification, and implementation teams.
Designs and optimizes high-speed digital logic for AMD’s mixed-signal IO interfaces, using Verilog RTL and ASIC flows to deliver silicon-ready solutions.
itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable,…
Junior Member of Technical Staff - AI Silicon Digital Design Engineer About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental…
About Unconventional Since 2022, AI has entered the mainstream, reshaping entire industries from education and software development to fundamental consumer behaviors. This revolution has created an unprecedented demand…
Senior engineer verifies memory controller IP for NVIDIA’s Tegra SoCs, building testbenches and performance tests to ensure functional correctness and speed across consumer, automotive, HPC, cloud, and AI products.
Senior Software Engineer at NVIDIA designing and developing tools for RTL generation and automated workflows in C++, with a focus on ASIC design and Verilog RTL for GPU and AI hardware.
Senior AI engineer building LLM-powered agents and RAG systems to automate SOC design workflows like design review, CI/CD gating, and cross-team reporting using Python, LangChain, and vector databases.
Senior engineer designing and integrating high-performance System-on-Chip (SOC) components for NVIDIA’s next-gen GPUs, using RTL design, automation, and scripting to streamline chip development.
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