Point your AI agent at freehire and let it find you a job. A CLI and an MCP server over the whole job API — no browser.
ASIC Design Verification Engineer responsible for owning verification strategy, coverage closure, and system-level testing for AMD’s mixed-signal power management IP, including RTL design and collaboration with analog/firmware teams.
Configure and integrate RISC processor IP into SoC platforms, customize processor features, develop RTL wrappers and system glue logic, integrate interconnects and interrupt controllers, support verification and system…
Lead physical design (RTL-to-GDS) for AMD’s next-gen AI and high-performance ASICs, driving PnR, timing closure, and tape-outs while collaborating with architects and EDA vendors.
Designs and implements RTL for SoC PAD/PFC logic (pin multiplexing, I/O control) using Verilog/SystemVerilog, in-house tools, and automation scripts to ensure design quality and integration.
Lead a team to architect and execute advanced verification strategies for next-gen semiconductor products using SystemVerilog, UVM, and emulation platforms.
Senior Design Verification Engineer at HPE focused on emulation-based verification of complex digital designs, building UVM/SystemVerilog testbenches and running designs on platforms like Palladium, ZeBu, and Veloce.
Lead RTL development of AI-enabled RISC-V CPU cores and matrix engines at a semiconductor foundry, covering microarchitecture, vector/matrix datapath design, and verification using SystemVerilog/Verilog.
We are now looking for a Senior CPU Design Methodology Engineer! The complexity of chip development has greatly increased over the years. We are now packing tens of billions of transistors in a chip to meet the growing…
About X X Corporation (Nasdaq: X), a market leader in MEMS timing, offers MEMS-based silicon timing system solutions. X configurable solutions offer a rich feature set that enables customers to differentiate their…
Lead ASIC RTL Design Engineer — Remote (U.S.) - No visa sponsorship Role Summary Our client, a leader in AI Compute is seeking a senior-level ASIC design engineer to drive the development of high-performance silicon…
DFT (Design for Testability) Engineer Role Summary: We are seeking a DFT Engineer to design and implement testability structures for complex ASIC/SoC designs, ensuring high test coverage, manufacturing yield, and…
About GlobalFoundries GlobalFoundries (GF) is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology…
About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive…
Job Details: Job Description: About Altera At Altera™, our independence as the world’s largest pure ‑ play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than…
Designs and optimizes digital ASICs for next-gen semiconductor systems, handling RTL coding, synthesis, timing analysis, and validation in a high-tech Swiss engineering environment.
We are seeking a highly motivated Principal Engineer Design to lead the physical implementation and timing closure of advanced low-power SoCs targeting the IoT and MCU markets. This role offers the opportunity to drive…
We are seeking an experienced Senior Staff - SoC Architect with 8+ years of expertise in SoC architecture, microarchitecture development, RTL design, low-power methodologies, and post-silicon debug. The candidate will…
Lead FPGA firmware architecture for a portable SIGINT/EW platform, migrating GPU DSP algorithms to FPGA and optimizing real-time RF signal processing for defense missions.
Role Overview We are looking for a highly skilled RTL Designer to develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targeting AI, HPC, and Networking…
The selected candidate will play a critical role in the architecture, design, verification, and implementation of RTL solutions for mixed-signal subsystems and standalone IPs. The role involves developing robust…
We couldn't check your fit for this role — add a CV to your profile to see it next time.
