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Develops formal verification IP for hardware design using Verilog and SystemVerilog Assertions, focusing on industry-standard bus protocols like AXI or PCIe.
Designs and leads embedded software for high-speed systems (Linux/RTOS/bare-metal), integrating with FPGA SoCs and hardware for clients in aerospace, telecom, automotive, and other advanced tech sectors.
Designs, verifies, and implements RTL for power management ICs and SoCs, collaborating with architects and verification teams to deliver high-performance semiconductor solutions.
Lead verification of high-performance SRAM memory compilers and subsystems for Marvell’s chip IP, using UVM, C, and industry tools to ensure correctness and performance before silicon bring-up.
Designs and optimizes low-power, mixed-signal microcontroller chips from floorplan to GDSII tapeout using EDA tools like Innovus and Calibre.
Designs and implements physical layouts for large system-on-chip (SoC) designs, using tools like Innovus/ICC2 to ensure timing closure and physical verification for chips from 40nm down to 3nm and below.
Leads a global team to architect, design, and deliver complex multi-chiplet System-on-Chip (SoC) designs for enterprise and AI infrastructure, using RTL coding, IP integration, and verification flows.
Designs and implements digital ASICs for scientific instruments, focusing on low-power, radiation-aware systems for particle detectors and high-energy physics applications using SystemVerilog/Verilog and EDA tools.
Designs and demonstrates IT network monitoring solutions for enterprise clients, troubleshooting and customizing systems while collaborating with sales and technical teams.
Designs and implements digital logic and IP for AI chips or SoCs using Verilog/SystemVerilog, verifies functionality, and integrates IP into larger systems with front-end design flows.
Leads the full-chip integration methodology for FPGA and custom SoC programs, defining how IP, power, and signoff corners are integrated and verified across projects.
Role Overview As a Sr. Staff/Principal Custom Circuit Design Engineer at Velaura AI, you will lead the architecture, design, and optimization of high-performance, low-power standard cell libraries and custom digital…
Role Overview As a DFT Architect/Manager/Sr. Manager at Velaura AI, you will lead the definition, implementation, and execution of Design-for-Test strategies for next-generation AI and high-performance computing…
Role Overview As a Staff/Sr. Staff/Principal Physical Design Engineer at Velaura AI, you will be responsible for driving the physical implementation and sign-off of critical blocks for next-generation AI and…
Responsibilities In this role, the Digital Design SME will act as a Technical Advisor/Consultant to critical SI/SETA activities and serve as a primary interface between the Program customers/stakeholders, the technical…
Designs and automates the RTL-to-GDSII physical design flow for AI inference hardware, optimizing power, performance, and area while ensuring signoff compliance.
Designs and optimizes AI hardware blocks from synthesis to GDSII sign-off, focusing on PPA and timing closure for advanced process nodes in a fast-paced startup.
Designs and optimizes the physical layout of advanced SoC chips, including floorplanning, placement, routing, and verification for high-performance applications like AI and automotive systems.
Junior engineer designs and implements physical layouts for advanced SoC chips using P&R and synthesis flows, verifying designs and analyzing timing/power in a semiconductor-focused team.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence’s Information Security team is seeking an experienced Software Security Architect. This role will…
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