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Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment,…
The application window is expected to close on: 09/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you live…
Leads the design and analysis of high-speed, low-power memory blocks and data paths for Intel's latest CPUs in cutting-edge process technology.
Leads FPGA-based emulation and prototyping for microcontroller SoCs, enabling early software development and system validation while optimizing hardware/software workflows.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description: This position focus on developing digital central solutions for 3D-IC application. The role…
The application window is expected to close on: 08/31/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This role is hybrid in San Jose,…
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative…
RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: None TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible…
WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a…
Designs, implements, and tests FPGA-based electronics for robotic surgical systems, focusing on video processing, motor control, and high-speed communications.
Leads the setup and optimization of physical design (PD) flows and infrastructure for energy-efficient processors, using Cadence Tempus or Synopsys Primetime and scripting languages.
Develops and maintains software using C++ and STL in Pune, India, focusing on debugging and problem-solving with optional scripting in Python, Tcl, or Shell.
Leads physical design and chip-package co-design for advanced semiconductor products, focusing on bump planning, floorplanning, and package-aware implementation for chiplet-based SoCs in cutting-edge process nodes.
Designs and validates high-speed electrical interconnects for advanced semiconductor packages, using tools like Ansys HFSS and Cadence Sigrity to optimize signal and power integrity for chiplet-based systems.
Designs and verifies FPGA hardware for a defense project, writing RTL code in VHDL/Verilog and running simulations with tools like Vivado and Questa.
Senior engineer responsible for RTL-to-GDSII physical design of complex digital blocks, including high-speed interfaces and automotive modules, using advanced EDA tools and timing closure techniques.
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