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This role involves leading the post-silicon enablement and optimization of high-speed memory subsystems for Google's custom silicon. The engineer will develop critical initialization firmware and diagnostic software to ensure performance and reliability for the Pixel product portfolio.
Investigates and reverse-engineers hardware and software systems for legal and business disputes, such as patent litigation or trade secrets, using programming, electrical engineering, and embedded systems expertise.
Senior engineer designing and running lab tests for electric-vehicle powertrains, automating data collection with LabVIEW and NI hardware, and building high-voltage test rigs.
The AI/ML ASIC Architect will design and define architecture specifications for next-generation AI storage and accelerator solutions, focusing on I/O subsystems and high-performance interfaces like PCIe, CXL, and UCIe. The role involves collaborating with cross-functional teams to optimize performance, power, and area for large-scale LLM training and inference workloads.
The Senior Software Test Engineer will validate neural network operators and libraries for AI computational storage products using C++ and Python. The role involves performance benchmarking, numerical accuracy validation, and debugging across the compiler, runtime, and hardware stack.
Develops and debugs firmware for next-gen storage devices, working with PCIe, FPGA boards, and hardware in an Agile CI-driven environment.
Leads end-to-end validation of AI software stack (neural network operators, compilers, runtimes, memory management) to ensure correctness, scalability, and performance for a next-gen AI computational storage platform.
Designs and develops complex software for embedded and real-time systems, collaborating with senior engineers to deliver high-quality solutions for diverse projects.
Build and optimize ultra-low-latency ML inference pipelines for quantitative trading, tuning GPU/FPGA kernels and memory hierarchies to microsecond precision.
Designs real-time FPGA-based image processing hardware for AR/HUD systems in defense and automotive, bridging sensor data and computational optics with strict latency constraints.
Overview Microsoft is the world’s center of expertise on topological quantum computing. We are building a scaled, fault‑tolerant quantum computer grounded in topological qubits and integrated end‑to‑end with the Azure…
Leads FPGA fabric design optimization and research for AMD’s Adaptive & Embedded Computing Group, focusing on programmable logic improvements, yield enhancement, and collaboration with silicon teams to advance future product architectures.
Date Posted: 2026-08-21 Country: United States of America Location: US-CA-GOLETA-B01 ~ 6825 Cortona Dr ~ BLDG B01 Position Role Type: Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to…
Job Details: Job Description: We are seeking a highly organized and customer-focused Inside Sales Representative (ISR) to support our field sales team in delivering best-in-class service to our customers. In this role,…
The FPGA Design Engineer will develop and maintain FPGA designs, core system software, and drivers for new and existing products. The role involves the full development lifecycle, including requirements analysis, RTL design, verification using VHDL, and DSP software development in C.
About GF GlobalFoundries® Inc. (GF®) is one of the world's leading semiconductor manufacturers. GF redefines innovation and semiconductor manufacturing by developing and delivering feature-rich process technology…
The Product Marketing Manager will drive the growth of the ASIP Designer tool-suite in Europe by managing customer relationships, identifying new design opportunities, and collaborating with sales and product teams. The role requires deep expertise in semiconductor design, specifically FPGA/ASIC/SoC workflows and processor architectures.
The Hardware Engineering Technical Leader will manage the full lifecycle of hardware systems for service provider routers, including architecture, design, and validation. The role involves using Cadence/Allegro for schematic capture and collaborating with cross-functional teams on high-speed SERDES and system-level hardware development.
Architect factory-level Automated Test Equipment (ATE) for avionics and land mobile radio products, designing rack-and-stack test systems and writing instrument control code in Python, C++, or NI TestStand.
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