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Principal Digital Engineer designs and implements DFT/Scan for automotive PMIC chips, working with RTL, synthesis, ATPG, and test teams to meet ASIL-B/D requirements and validate patterns on silicon.
Principal Engineer defines and leads SoC/MCU architectures for India-focused semiconductor platforms, coordinating RTL design, verification, firmware, and validation to deliver first-pass silicon for automotive, industrial, and emerging domains.
Design and implement memory controllers, hierarchies, and near-memory accelerators for AI-driven ASICs, optimizing bandwidth, latency, and power for ML workloads using SystemVerilog and AI-assisted flows.
Design and own the on-chip interconnect fabric and high-speed I/O subsystems for AI-driven ASICs, implementing AMBA-compliant NoC routers, crossbars, and bridges to ensure low-latency, high-bandwidth data movement in production silicon.
Build AI-powered automation tools to streamline Arm’s hardware design and verification workflows, integrating EDA tools and AI models like OpenAI Codex to cut cycle time and debug effort.
Design and lead digital architectures for power-management ICs in automotive and industrial systems using Verilog/SystemVerilog, synthesis, and verification flows.
Principal Engineer to lead digital design, synthesis, and static timing analysis for high-speed ICs at advanced process nodes using Cadence/Synopsys tools.
Leads hardware/software co-verification for SoC devices using emulators (e.g., Cadence Palladium) and FPGAs, bridging RTL porting, firmware development, and system-level testing across pre- and post-silicon phases.
Architect and deploy hardware emulation platforms for next-gen HBM memory products, integrating AI-driven tools to accelerate pre-silicon validation and firmware bring-up.
Architect and lead validation of next-gen memory subsystems (DDR5, LPDDR5/6, HBM) for FPGAs, defining scalable methodologies and driving silicon bring-up, debug, and customer enablement.
Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description - 5+ year RTL designer We are looking for a highly motivated RTL Design…
Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual independently plans, performs the moderately-defined responsibility for the digital…
At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is…
Lead pre-silicon verification of semiconductor IPs and SoCs using UVM, SystemVerilog, and industry simulators to ensure functional correctness before tape-out.
Graduate trainee develops FPGA IP cores using HDL, RTL design, and verification, working with tools like Vivado/Quartus and collaborating on real-world FPGA-based system projects.
Design-for-Test engineer implementing scan, MBIST, JTAG, and ATPG flows to improve SoC test coverage and silicon yield while collaborating with cross-functional teams.
Junior DFT engineer at NXP developing automotive and industrial SoCs; writes RTL, implements scan/ATPG/MBIST test flows, and automates validation using scripting and AI.
Lead a team designing and implementing next-generation networking ASICs, guiding RTL development, implementation, and tapeout while collaborating with cross-functional teams to meet performance and schedule targets.
Job Details: Job Description: Physical Design and Implementation Lead, Memory PHY IP (DDR/LPDDR) Intel is seeking an experienced Senior Director of Engineering to lead the Physical Design organization responsible for…
Lead a team designing and implementing high-performance networking ASICs from architecture to tapeout, collaborating with cross-functional teams to deliver silicon for HPE's networking products.
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