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Build and lead a new automation platform for SoC chassis design, translating architecture specs into generated RTL, registers, and verification collateral using Python and templating systems.
We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis…
Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual leads the team to improve engineering efficiency, product quality and…
As a Senior Design Engineer, you will be responsible for all aspects of front-end ASIC design, including RTL implementation and verification of complex logic blocks. You will collaborate with PD, DFT, STA, and…
Designs and integrates custom ASICs for Apple’s SoCs using SystemVerilog, RTL, and synthesis while collaborating with hardware and software teams.
Lead FPGA design engineer develops, debugs, and tests firmware and software for embedded systems, collaborating with cross-functional teams to deliver robust hardware solutions for industrial and smart-energy applications.
Design and verify digital logic for novel AI hardware using SystemVerilog, collaborating across architecture, verification, and physical design to tape out custom ASICs.
Leads verification of next-gen RISC-V processor IP using SystemVerilog/UVM, ensuring functional correctness and silicon readiness for GlobalFoundries' semiconductor products.
Intern designs and verifies low-power digital ICs using SystemVerilog/Verilog, simulates MCUs, and prototypes designs on FPGA.
Lead the full lifecycle of NVIDIA’s next-gen switch ASICs, coordinating RTL design, verification, physical design, and post-silicon bring-up with cross-functional teams.
Designs and implements reusable digital IP blocks (Verilog/SystemVerilog) for low-power wireless SoCs, focusing on PPA targets and AMBA/peripheral IP like SPI, UART, and DMA.
Designs and verifies System-on-Chip (SoC) subsystems using Verilog/SystemVerilog, integrating high-speed IPs like PCIe and DDR, and collaborating with verification and backend teams.
Our vision is to transform how the world uses information to enrich life for all . Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into…
Senior ASIC engineer designing on-chip interconnects and last-level caches for NVIDIA’s CPU and AI platforms, focusing on synthesis, timing closure, and performance optimization.
Engineer scalable compilation and synthesis flows for NVIDIA’s hardware emulation platforms, using EDA tools like Synopsys and Cadence to validate complex chip designs before fabrication.
Designs and implements high-performance processor cores and SoC subsystems using Verilog/SystemVerilog, driving microarchitecture, RTL coding, and PPA optimization from concept to silicon bring-up.
Leads a team to design and tape out next-gen processor and SoC IP, guiding RTL development, verification, and PPA optimization for high-performance, low-power ASICs.
Job Details: Job Description: Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled team developing cutting-edge silicon for GenAI workloads, where we push the…
Design and implement synthesizable RTL for complex ASICs using Verilog/SystemVerilog, optimizing for power, performance, and area while collaborating with verification and physical design teams.
Designs and verifies GPU and control subsystems for AI-focused SoCs, integrating Arm IP and third-party components for edge, physical, and cloud AI applications.
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