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The Infrastructure Architect will lead the modernization and operation of compute platforms, transitioning legacy monolith systems to cloud-native environments using Azure, AWS, and Kubernetes. The role involves designing scalable infrastructure, automating processes, and providing technical consultation to stakeholders.
Design and maintain cloud-based data pipelines, warehouses, and lakes for a large bank, ensuring secure, accurate, and high-velocity data processing and enabling analytics and ML workflows.
NVIDIA is seeking interns for a 12-week digital circuit design program focused on hardware development for accelerated computing. Interns will work on projects involving circuit design, simulation, and optimization using tools like Verilog, Python, and industry-standard EDA software.
A 12-week full-time internship in Mixed-Signal Design at NVIDIA, where students contribute to hardware projects impacting industries like AI, robotics, and healthcare. Core focus: analog circuit design, simulation, and hardware testing.
NVIDIA is seeking interns for a 12-week hardware verification program to work on projects involving GPU and processor architecture, functional testing, and digital design. Interns will utilize tools like SystemVerilog, UVM, and various simulation environments to support hardware validation efforts.
NVIDIA is seeking interns for their Deep Learning Computer Architecture teams to work on projects involving GPU/CPU architecture, performance modeling, and parallel programming. Interns will utilize technologies such as C++, CUDA, and deep learning frameworks to solve complex computing challenges.
NVIDIA is seeking Ph.D. students for hardware research internships focused on circuit design, ASIC/VLSI development, and electronic design automation (EDA). Interns will collaborate with research teams to develop prototypes and publish original research in areas like ML accelerators, memory design, and high-speed signaling.
NVIDIA is seeking interns for 12-week roles in hardware physical design and VLSI, focusing on chip implementation, timing closure, and physical verification using industry-standard EDA tools. Interns will work on projects impacting accelerated computing, AI, and robotics while pursuing their degree.
NVIDIA is seeking interns for 12-week hardware ASIC design roles, focusing on tasks like RTL design, verification, and physical design. Interns will work on projects impacting AI, robotics, and accelerated computing using tools like SystemVerilog, C++, and Python.
NVIDIA is seeking interns for 12-week roles focused on deep learning applications, algorithms, and framework development. Interns will work on GPU-accelerated computing projects using technologies like CUDA, PyTorch, and TensorFlow.
NVIDIA is seeking M.S. or Ph.D. students for a 12-week Hardware Design for Test (DFT) internship. Interns will work on hardware testing architectures, digital design, and silicon debug using tools like Synopsys and Cadence.
NVIDIA offers 12-week hardware engineering internships for students pursuing degrees in electrical or computer engineering. Interns work on projects across system validation, hardware design, mechanical engineering, and silicon solutions using tools like Python, Verilog, and various CAD software.
Job Title: Senior Cyber Automation Engineer - ISSE Job Category: Engineering Time Type: Full time Minimum Clearance Required to Start: TS/SCI with Polygraph Employee Type: Regular Percentage of Travel Required: Up to…
Analyzes complex biological and oncology datasets using computational tools like R and Python to process, visualize, and interpret high-throughput genomic/proteomic data, develop bioinformatics pipelines, and support cancer research projects.
Job Overview: Are you an RTL engineer eager to build expertise across multiple IP products? Do you want to work globally with internal teams to develop systems optimized for performance and power? If so, we want to…
This senior technical role involves architecting and maintaining complex build, configuration, and release systems for embedded software products. The role requires deep expertise in C/C++ build toolchains and infrastructure to support large-scale, distributed engineering teams.
Tier 1 Systems Administrator supporting classified U.S. Space Force lab infrastructure in Boulder, CO. Daily tasks include onsite hardware/network/storage administration, troubleshooting, AD management, vendor onboarding, and event IT/AV support in a Red Hat/Windows environment with security clearance requirements.
Principal FPGA Design Engineer at Microchip's Chandler Design Center developing and validating FPGA-based platforms for next-gen USB and Ethernet PHY products using Verilog/SystemVerilog RTL design, Vivado, and lab debug equipment.
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