RD Team_Sr. Physical Digital Design Engineer_資深數位IC實體設計工程師 (台北)

Job Summary:
The Sr. Physical Digital Design Engineer will be responsible for all aspects of physical design and implementation. In this role, you will participate in the efforts of establishing physical design methodologies and flow automation.

The candidate will work on the digital design implementation, and verification of mixed-signal ICs utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions.

Products: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as broadband modems, notebooks, cell phones, telecom, fiber optics, digital camera, automobile and network equipment.

Essential Functions:

• Responsible for physical design, development, & verification of digital / mixed-signal IC's
• Chip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closure
• Work closely with digital/analog design team for physical implementation and custom analog blocks/interface/IP's
• Help build an automated environment for RTL-to-PNR using high level languages and DevOps-like services

Qualifications:

• MS/BS in Electrical Engineering or equivalent.
• 5-8 years or above experience of Physical Digital Design experience.
• Strong knowledge of ASIC development process and digital design techniques.
• Strong technical abilities & understanding in these areas:

1. Synthesis, LEC, CTS, DFT, RC Extraction, and STA closure across multiple process corners.
2. Multi-power domain, signal integrity, & power/IR drop analysis.
3. Expertise in both hand-written and tool-driven functional/timing ECO.
4. Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.
5. Industry physical tools: Cadence (preferred) or Synopsys.

• Experience with the following is desired:

1. Advanced nodes below 16nm
2. SOC design including uC design (ARM/RISCV)
3. Digital on top designs using both bottom-up and top-down flows
4. Hierarchical STA for chip top designs
5. STA, AOCV, SI closure
6. Knowledge of power management industry/applications
7. I/F: I2C, SPI, USB, PMBUS, etc
8. Advanced DFT techniques: LBIST, Delay Fault, SCAN Compression, MBIST etc.

• Good written/verbal communication English skills and strong teamwork collaboration
• Ability to work independently, follow instructions according to design specifications and execute tasks to hit milestones with quality.
• Experience with programming, scripting and automation languages like Perl/Python/TCL/Unix